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22 - s3 - f441fx - 022001 user's manual S3F441FX 32 -bit cmos risc micro processor revision 2
S3F441FX 32-bit risc microprocessors user's manual revision 2
ii S3F441FX risk micro processors important notice the information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. this publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of samsung or others. samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including " typicals" must be validated for each customer application by the customer's technical experts. samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the samsung product could create a situation where personal injury or death may occur. should the buyer purchase or use a samsung product for any such unintended or unauthorized application, the buyer shall indemnify and hold samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that samsung was negligent regarding the design or manufacture of said product. S3F441FX risc microprocessors user's manual, revision 2 publication number: 22-s3-c441fx-022001 ? 2001 samsung electronics all rights reserved. no part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of samsung electronics. samsung electronics' microprocessor business has been awarded full iso- 14001 certification (bsi certificate no. fm24653). all semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. samsung electronics co., ltd. san #24 nongseo-ri, kiheung-eup yongin-city, kyunggi-do, korea c.p.o. box #37, suwon 449-900 tel: (82)-(031)-209-1907 fax: (82)-(031)-209-1899 home-page url: http:// www.intl.samsungsemi.com printed in the republic of korea
S3F441FX risk microprocessors iii preface the S3F441FX risc microprocessor user's manual is designed specifically for application designers and programmers who are using S3F441FX risc microprocessor for product development. section 1, 'product overview,' is a high-level introduction to the S3F441FX and includes a features list, block diagram, pin assignments, signal descriptions, a description of the cpu core, and an overview of special registers. section 2, 'programmer?s model', describes the important features of the S3F441FX programming environment. section 3, 'instruction set', describes the features of the S3F441FX instruction set, which is based on a cpu core developed by arm, ltd. section 4, 'i/o ports', describes the S3F441FX input/output ports and special function registers. section 5, 'basic timer/watchdog timer', describes the basic timer & watch-dog timer, including a interval mode operation, and special function registers. section 6, 'timer module 0,1,2,3,4,5 (16-bit timers)', describes the timer modules, including a operation modes and special function registers. section 7, 'uart', describes the uart function blocks, including uart operation, special function registers, and timing. section 8, 'interrupt controller', describes the interrupt source and special function registers. section 9, 'system manager', describes the system manager function block which consists of registers that control bus arbitration and management, as well as external memory access and timing. section 10, 'internal flash rom', describes the internal flash rom function blocks, including the internal flash rom operation and special function registers. section 11, 'system control', describes the power-down mode and pll (phase locked loop) function blocks, including operation modes and special function registers. section 12, 'special function registers', describes all the S3F441FX special function registers. in each of these sections, you will find detailed descriptions of the special registers that are associated with each function block. these descriptions orient you to the block's features and also serve as a quick reference when writing application code. the remaining sections of this manual, sections 13 and 14, present d.c. and a.c. electrical characteristics and related timing diagrams and mechanical data for 64-pin lqfp package of the S3F441FX.

S3F441FX risc microprocessor v table of contents chapter 1 product ove rview introduction ................................ ................................ ................................ ................................ .............. 1-1 features ................................ ................................ ................................ ................................ .................. 1-2 block diagram ................................ ................................ ................................ ................................ ......... 1-3 pin assignments ................................ ................................ ................................ ................................ ...... 1-4 signal descriptions ................................ ................................ ................................ ................................ .. 1-5 i/o pin types ................................ ................................ ................................ ................................ ........... 1-7 chapter 2 programmer's model overview ................................ ................................ ................................ ................................ ................. 2-1 processor operating states ................................ ................................ ................................ ..................... 2-1 switching state ................................ ................................ ................................ ................................ ........ 2-1 memory formats ................................ ................................ ................................ ................................ ..... 2-1 big-endian format ................................ ................................ ................................ ................................ ... 2-2 little-endian format ................................ ................................ ................................ ................................ 2-2 instruction length ................................ ................................ ................................ ................................ .... 2-2 operating modes ................................ ................................ ................................ ................................ ..... 2-3 registers ................................ ................................ ................................ ................................ ................. 2-3 the program status registers ................................ ................................ ................................ ................. 2-7 exceptions ................................ ................................ ................................ ................................ ............... 2-10 interrupt latencies ................................ ................................ ................................ ................................ ... 2-15 reset ................................ ................................ ................................ ................................ ....................... 2-15 chapter 3 instruction set instruction set summay ................................ ................................ ................................ ........................... 3-1 format summary ................................ ................................ ................................ ............................ 3-1 instruction summary ................................ ................................ ................................ ....................... 3-2 the condition field ................................ ................................ ................................ ................................ . 3-4 branch and exchange (bx) ................................ ................................ ................................ ...................... 3-5 instruction cycle times ................................ ................................ ................................ ................... 3-5 assembler syntax ................................ ................................ ................................ ........................... 3-5 using r15 as an operand ................................ ................................ ................................ ............... 3-5 examples ................................ ................................ ................................ ................................ ........ 3-6 branch and branch with link (b, bl) ................................ ................................ ................................ ...... 3-7 the link bit ................................ ................................ ................................ ................................ ..... 3-7 instruction cycle times ................................ ................................ ................................ ................... 3-7 assembler syntax ................................ ................................ ................................ ........................... 3-8 examples ................................ ................................ ................................ ................................ ........ 3-8
vi S3F441FX risc micro processor table of contents (continued) chapter 3 instruction set (continued) data processing ................................ ................................ ................................ ................................ ....... 3-9 cpsr flags ................................ ................................ ................................ ................................ .... 3-11 shifts ................................ ................................ ................................ ................................ ............... 3-12 immediate operand rotates ................................ ................................ ................................ ............ 3-16 writing to r15 ................................ ................................ ................................ ................................ . 3-16 using r15 as an operandy ................................ ................................ ................................ .............. 3-16 teq, tst, cmp and cmn opcodes ................................ ................................ ................................ . 3-16 instruction cycle times ................................ ................................ ................................ ................... 3-16 assembler syntax ................................ ................................ ................................ ........................... 3-17 examples ................................ ................................ ................................ ................................ ........ 3-17 psr transfer (mrs, msr) ................................ ................................ ................................ ........................ 3-18 operand restrictions ................................ ................................ ................................ ....................... 3-18 reserved bits ................................ ................................ ................................ ................................ .. 3-20 instruction cycle times ................................ ................................ ................................ ................... 3-20 assembly syntax ................................ ................................ ................................ ............................. 3-21 examples ................................ ................................ ................................ ................................ ........ 3-21 multiply and multiply-accumulate (mul, mla) ................................ ................................ ......................... 3-22 cpsr flags ................................ ................................ ................................ ................................ .... 3-24 instruction cycle times ................................ ................................ ................................ ................... 3-24 assembler syntax ................................ ................................ ................................ ........................... 3-24 examples ................................ ................................ ................................ ................................ ........ 3-24 multiply long and multiply-accumulate long (mull, mlal) ................................ ................................ .... 3-25 operand restrictions ................................ ................................ ................................ ....................... 3-26 cpsr flags ................................ ................................ ................................ ................................ .... 3-26 instruction cycle times ................................ ................................ ................................ ................... 3-26 assembler syntax ................................ ................................ ................................ ........................... 3-27 examples ................................ ................................ ................................ ................................ ........ 3-27 single data transfer (ldr, str) ................................ ................................ ................................ ............. 3-28 offsets and auto-indexing ................................ ................................ ................................ ............... 3-29 shifted register offset ................................ ................................ ................................ .................... 3-29 bytes and words ................................ ................................ ................................ ............................. 3-29 use of r15 ................................ ................................ ................................ ................................ ...... 3-31 restriction on the use of base register ................................ ................................ ......................... 3-31 data aborts ................................ ................................ ................................ ................................ ..... 3-31 instruction cycle times ................................ ................................ ................................ ................... 3-31 assembler syntax ................................ ................................ ................................ ........................... 3-32 examples ................................ ................................ ................................ ................................ ........ 3-33 halfword and signed data transfer (ldrh/strh/ldrsb/ldrsh) ................................ ........................ 3-34 offsets and auto-indexing ................................ ................................ ................................ ............... 3-35 halfword load and stores ................................ ................................ ................................ ............... 3-36 signed byte and halfword loads ................................ ................................ ................................ ..... 3-36 endianness and byte/halfword selection ................................ ................................ ........................ 3-36 use of r15 ................................ ................................ ................................ ................................ ...... 3-37 data aborts ................................ ................................ ................................ ................................ ..... 3-37 instruction cycle times ................................ ................................ ................................ ................... 3-37 assembler syntax ................................ ................................ ................................ ........................... 3-38 examples ................................ ................................ ................................ ................................ ........ 3-39
S3F441FX risc microprocessor vii table of contents (continued) chapter 3 instruction set (continued) block data transfer (ldm, stm) ................................ ................................ ................................ ............. 3-40 the register list ................................ ................................ ................................ ............................. 3-40 addressing modes ................................ ................................ ................................ ........................... 3-41 address alignment ................................ ................................ ................................ .......................... 3-41 use of the s bit ................................ ................................ ................................ .............................. 3-43 use of r15 as the base ................................ ................................ ................................ ................. 3-43 inclusion of the base in the register list ................................ ................................ ....................... 3-44 data aborts ................................ ................................ ................................ ................................ ..... 3-44 instruction cycle times ................................ ................................ ................................ ................... 3-44 assembler syntax ................................ ................................ ................................ ........................... 3-45 examples ................................ ................................ ................................ ................................ ........ 3-46 single data swap (swp) ................................ ................................ ................................ ......................... 3-47 bytes and words ................................ ................................ ................................ ............................. 3-47 use of r15 ................................ ................................ ................................ ................................ ...... 3-48 data aborts ................................ ................................ ................................ ................................ ..... 3-48 instruction cycle times ................................ ................................ ................................ ................... 3-48 assembler syntax ................................ ................................ ................................ ........................... 3-48 examples ................................ ................................ ................................ ................................ ........ 3-48 software interrupt (swi) ................................ ................................ ................................ .......................... 3-49 return from the supervisor ................................ ................................ ................................ ........... 3-49 comment field ................................ ................................ ................................ ................................ 3-49 instruction cycle times ................................ ................................ ................................ ................... 3-49 assembler syntax ................................ ................................ ................................ ........................... 3-50 examples ................................ ................................ ................................ ................................ ........ 3-50 coprocessor data operations (cdp) ................................ ................................ ................................ ....... 3-51 coprocessor instructions ................................ ................................ ................................ ................. 3-51 instruction cycle times ................................ ................................ ................................ ................... 3-52 assembler syntax ................................ ................................ ................................ ........................... 3-52 examples ................................ ................................ ................................ ................................ ........ 3-52
viii S3F441FX risc micro processor table of contents (continued) chapter 3 instruction set (continued) coprocessor data transfers (ldc, stc) ................................ ................................ ................................ . 3-53 the coprocessor fields ................................ ................................ ................................ ................... 3-53 addressing modes ................................ ................................ ................................ ........................... 3-54 address alignment ................................ ................................ ................................ .......................... 3 -54 use of r15 ................................ ................................ ................................ ................................ ...... 3-54 data aborts ................................ ................................ ................................ ................................ ..... 3-54 instruction cycle times ................................ ................................ ................................ ................... 3-54 assembler syntax ................................ ................................ ................................ ........................... 3-55 examples ................................ ................................ ................................ ................................ ........ 3-55 coprocessor register transfers (mrc, mcr) ................................ ................................ ................. 3-56 the coprocessor fields ................................ ................................ ................................ ................... 3-56 transfers to r15 ................................ ................................ ................................ .............................. 3-57 transfers from r15 ................................ ................................ ................................ ......................... 3-57 instruction cycle times ................................ ................................ ................................ ................... 3-57 assembler syntax ................................ ................................ ................................ ........................... 3-57 examples ................................ ................................ ................................ ................................ ........ 3-57 undefined instruction ................................ ................................ ................................ ....................... 3-58 instruction cycle times ................................ ................................ ................................ ................... 3-58 assembler syntax ................................ ................................ ................................ ........................... 3-58 instruction set examples ................................ ................................ ................................ ................. 3-59 using the conditional instructions ................................ ................................ ................................ ... 3-59 pseudo-random binary sequence generator ................................ ................................ ................. 3-61 multiplication by constant using the barrel shifter ................................ ................................ ......... 3-61 loading a word from an unknown alignment ................................ ................................ ................. 3-63 thumb instruction set format ................................ ................................ ................................ .................. 3-65 format summary ................................ ................................ ................................ ............................ 3-65 opcode summary ................................ ................................ ................................ ........................ 3-66
S3F441FX risc microprocessor ix table of contents (continued) chapter 3 instruction set (continued) format 1: move shifted register ................................ ................................ ................................ ............. 3-68 operation ................................ ................................ ................................ ................................ ........ 3-68 instruction cycle times ................................ ................................ ................................ ................... 3-69 examples ................................ ................................ ................................ ................................ ........ 3-69 format 2: add/subtract ................................ ................................ ................................ ............................ 3-70 operation ................................ ................................ ................................ ................................ ........ 3-70 instruction cycle times ................................ ................................ ................................ ................... 3-71 examples ................................ ................................ ................................ ................................ ........ 3-71 format 3: move/compare/add/subtract immediate ................................ ................................ ................. 3-72 operations ................................ ................................ ................................ ................................ ...... 3-72 instruction cycle times ................................ ................................ ................................ ................... 3-73 examples ................................ ................................ ................................ ................................ ........ 3-73 format 4: alu operations ................................ ................................ ................................ ......................... 3-74 operation ................................ ................................ ................................ ................................ ........ 3-74 instruction cycle times ................................ ................................ ................................ ................... 3-75 examples ................................ ................................ ................................ ................................ ........ 3-75 format 5: hi-register operations/branch exchange ................................ ................................ ................ 3-76 operation ................................ ................................ ................................ ................................ ........ 3-76 instruction cycle times ................................ ................................ ................................ ................... 3-77 the bx instruction ................................ ................................ ................................ ........................... 3-77 examples ................................ ................................ ................................ ................................ ........ 3-78 using r15 as an operand ................................ ................................ ................................ ............... 3-78 format 6: pc-relative load ................................ ................................ ................................ ..................... 3-79 operation ................................ ................................ ................................ ................................ ........ 3-79 instruction cycle times ................................ ................................ ................................ ................... 3-80 examples ................................ ................................ ................................ ................................ ........ 3-80 format 7: load/store with register offset ................................ ................................ .............................. 3-81 operation ................................ ................................ ................................ ................................ ........ 3-82 instruction cycle times ................................ ................................ ................................ ................... 3-82 examples ................................ ................................ ................................ ................................ ........ 3-82 format 8: load/store sign-extended byte/halfword ................................ ................................ ................ 3 -83 operation ................................ ................................ ................................ ................................ ........ 3-83 instruction cycle times ................................ ................................ ................................ ................... 3-84 examples ................................ ................................ ................................ ................................ ........ 3-84 format 9: load/store with immediate offset ................................ ................................ .......................... 3-85 operation ................................ ................................ ................................ ................................ ........ 3-85 instruction cycle times ................................ ................................ ................................ ................... 3-86 examples ................................ ................................ ................................ ................................ ........ 3-86 format 10: load/store halfword ................................ ................................ ................................ .............. 3-87 operation ................................ ................................ ................................ ................................ ........ 3-87 examples ................................ ................................ ................................ ................................ ........ 3-88 format 11: sp-relative load/store ................................ ................................ ................................ .......... 3-89 operation ................................ ................................ ................................ ................................ ........ 3-89 instruction cycle times ................................ ................................ ................................ ................... 3-89 examples ................................ ................................ ................................ ................................ ........ 3-89
x S3F441FX risc micro processor table of contents (continued) chapter 3 instruction set (continued) format 12: load address ................................ ................................ ................................ ......................... 3-90 operation ................................ ................................ ................................ ................................ ........ 3-90 instruction cycle times ................................ ................................ ................................ ................... 3-91 examples ................................ ................................ ................................ ................................ ........ 3-91 format 13: add offset to stack pointer ................................ ................................ ................................ .. 3-92 operation ................................ ................................ ................................ ................................ ........ 3-92 instruction cycle times ................................ ................................ ................................ ................... 3-92 examples ................................ ................................ ................................ ................................ ........ 3-92 format 14: push/pop registers ................................ ................................ ................................ ............... 3-93 operation ................................ ................................ ................................ ................................ ........ 3-93 instruction cycle times ................................ ................................ ................................ ................... 3-94 examples ................................ ................................ ................................ ................................ ........ 3-94 format 15: multiple load/store ................................ ................................ ................................ ................ 3-95 operation ................................ ................................ ................................ ................................ ........ 3-95 instruction cycle times ................................ ................................ ................................ ................... 3-95 examples ................................ ................................ ................................ ................................ ........ 3-95 format 16: conditional branch ................................ ................................ ................................ ................ 3-96 operation ................................ ................................ ................................ ................................ ........ 3-96 instruction cycle times ................................ ................................ ................................ ................... 3-97 examples ................................ ................................ ................................ ................................ ........ 3-97 format 17: software interrupt ................................ ................................ ................................ .................. 3-98 operation ................................ ................................ ................................ ................................ ........ 3-98 instruction cycle times ................................ ................................ ................................ ................... 3-98 examples ................................ ................................ ................................ ................................ ........ 3-98 format 18: unconditional branch ................................ ................................ ................................ ............. 3-99 operation ................................ ................................ ................................ ................................ ........ 3-99 examples ................................ ................................ ................................ ................................ ........ 3-99 operation ................................ ................................ ................................ ................................ ........ 3-100 instruction cycle times ................................ ................................ ................................ ............................ 3-101 examples ................................ ................................ ................................ ................................ ........ 3-101 instruction set examples ................................ ................................ ................................ ......................... 3-102 multiplication by a constant using shifts and adds ................................ ................................ ........ 3-102 general purpose signed divide ................................ ................................ ................................ ....... 3-103 division by a constant ................................ ................................ ................................ .................... 3-105
S3F441FX risc microprocessor xi table of contents (continued) chapter 4 memory controller overview ................................ ................................ ................................ ................................ ................. 4-1 port data registers ................................ ................................ ................................ ......................... 4-2 port control registers table ................................ ................................ ................................ ........... 4-2 chapter 5 basic/watchdog timer overview ................................ ................................ ................................ ................................ ................. 5-1 basic timer counter register ................................ ................................ ................................ .......... 5-2 external oscillation stabilization time after stop or reset ................................ .............................. 5-2 watch dog timer counter ................................ ................................ ................................ ............... 5-2 basic timer control register ................................ ................................ ................................ ........... 5-3 function description ................................ ................................ ................................ ................................ 5-4 interval timer function ................................ ................................ ................................ ................... 5-4 chapter 6 timer module 0,1,2,3,4,5 (16-bit timers) overview ................................ ................................ ................................ ................................ ................. 6-1 timer 0,1,2,3,4,5 control registers (t0con,t1con,t2con,t3con,t4con,t5con) .......................... 6-3 interval mode operation ................................ ................................ ................................ .................. 6-3 capture mode operation ................................ ................................ ................................ ................. 6-4 match & overflow mode operation ................................ ................................ ................................ .. 6-4 timer special registers ................................ ................................ ................................ ........................... 6-5 timer control registers ................................ ................................ ................................ ................... 6-5 timer data registers ................................ ................................ ................................ ...................... 6-7 timer count registers ................................ ................................ ................................ ..................... 6-8 timer pre-scaler registers ................................ ................................ ................................ .............. 6-9 chapter 7 u art overview ................................ ................................ ................................ ................................ ................. 7-1 infra-red mode ................................ ................................ ................................ ............................... 7-3 uart special registers ................................ ................................ ................................ .......................... 7-4 uart line control register ................................ ................................ ................................ ............ 7-4 uart control register ................................ ................................ ................................ .................... 7-6 uart status register ................................ ................................ ................................ ..................... 7-8 uart transmit buffer register ................................ ................................ ................................ ....... 7-10 uart receive buffer register ................................ ................................ ................................ ........ 7-11 uart baud rate prescaler registers ................................ ................................ ............................. 7-12
xii S3F441FX risc micro processor table of contents (continued) chapter 8 interrupt controller overview ................................ ................................ ................................ ................................ ................. 8-1 interrupt sources ................................ ................................ ................................ ................................ ..... 8-3 interrupt controller special registers ................................ ................................ ................................ ....... 8-4 interrupt mode register ................................ ................................ ................................ ................... 8-4 interrupt pending register ................................ ................................ ................................ ............... 8-5 interrupt mask register ................................ ................................ ................................ ................... 8-6 chapter 9 system manage r overview ................................ ................................ ................................ ................................ ................. 9-1 system manager registers ................................ ................................ ................................ ...................... 9-2 system register address configuration register (syscfg) ................................ ........................... 9-4 external memory control special registers ................................ ................................ ............................. 9-5 memory control register 0, 1, 2 ................................ ................................ ................................ ...... 9-5 chapter 10 internal flash rom overview ................................ ................................ ................................ ................................ ................. 10-1 programming modes ................................ ................................ ................................ ................................ 10-2 flash memory special registers ................................ ................................ ................................ .............. 10-4 flash memory key registers ................................ ................................ ................................ ............... 10-4 flash memory address register ................................ ................................ ................................ .......... 10-4 flash memory data register ................................ ................................ ................................ ............... 10-4 flash memory user programming control register ................................ ................................ ............. 10-5 flash memory error register ................................ ................................ ................................ ............... 10-6 flash memory smart option bits read register ................................ ................................ .................. 10-7 flash memory protection option bits read register ................................ ................................ ............ 10-7 data protection ................................ ................................ ................................ ................................ ........ 10-10 protection option ................................ ................................ ................................ ................................ . 10-10 smart option for ldc protection / h/w protection ................................ ................................ ............. 10-12 flash memory map ................................ ................................ ................................ ................................ .. 10-13 tool program mode ................................ ................................ ................................ ................................ . 10-14
S3F441FX risc microprocessor xiii table of contents (concluded) chapter 11 system control power-down mode ................................ ................................ ................................ ................................ .. 11-1 global interrupt control ................................ ................................ ................................ ....................... 11-1 pll ................................ ................................ ................................ ................................ ..................... 11-1 entering the stop mode ................................ ................................ ................................ ...................... 11-2 exiting from the stop mode ................................ ................................ ................................ ............... 11-2 idle mode and internal flash rom ................................ ................................ ................................ ...... 11-2 system control register ................................ ................................ ................................ ...................... 11-3 pll (phase locked loop) ................................ ................................ ................................ .................... 11-4 pll control register (pllcon) ................................ ................................ ................................ .......... 11-5 pll value selection guide ................................ ................................ ................................ .................. 11-5 pll value change steps ................................ ................................ ................................ ..................... 11-5 capacitor for pll loop filter ................................ ................................ ................................ ................. 11-5 chapter 12 special function registers overview ................................ ................................ ................................ ................................ ................. 12-1 S3F441FX special registers ................................ ................................ ................................ ................... 12-2 chapter 13 electrical data dc electrical characteristics ................................ ................................ ................................ ................... 13-1 ac electrical characteristics ................................ ................................ ................................ .................... 13-5 chapter 14 mechanical data package dimensions ................................ ................................ ................................ ............................... 14-1

S3F441FX risc microprocessor xv list of figures figure title page number number 1-1 S3F441FX block diagram ................................ ................................ ...................... 1-3 1-2 S3F441FX pin assignments (64-lqfp) ................................ ................................ . 1-4 1-3 iopuse (schmitt input/output pin w ith programmable pull-up resistor and edge detection) ................................ ................................ ............................... 1-8 1-4 iopus (schmitt input/output pin with programmable pull-up resistor) ................. 1-8 1-5 iopd (input/output pin with programmable pull-down resistor) ............................ 1-9 1-6 iopu (input/output pin with programmable pull-up resistor) ................................ . 1-9 2-1 big-endian addresses of bytes within words ................................ ......................... 2-2 2-2 little-endian addresses of bytes within words ................................ ....................... 2-2 2-3 register organization in arm state ................................ ................................ ....... 2-4 2-4 register organization in thumb state ................................ ................................ ... 2-5 2-5 mapping of thumb state registers onto arm s tate registers .............................. 2-6 2-6 program status register format ................................ ................................ ............ 2-7 3-1 arm instruction set format ................................ ................................ ................... 3-1 3-2 branch and exchange instructions ................................ ................................ ......... 3-5 3-3 branch instructions ................................ ................................ ................................ . 3-7 3-4 data processing instructions ................................ ................................ .................. 3-9 3-5 arm shift operations ................................ ................................ ............................. 3-12 3-6 logical shift left ................................ ................................ ................................ .... 3-12 3-7 logical shift right ................................ ................................ ................................ .. 3-13 3-8 arithmetic shift right ................................ ................................ ............................. 3-13 3-9 rotate right ................................ ................................ ................................ ........... 3-14 3-10 rotate right extended ................................ ................................ ........................... 3-14 3-11 psr transfer ................................ ................................ ................................ ......... 3-19 3-12 multiply instructions ................................ ................................ ................................ 3-22 3-13 multiply long instructions ................................ ................................ ....................... 3-25 3-14 single data transfer instructions ................................ ................................ ............ 3-28 3-15 little-endian offset addressing ................................ ................................ .............. 3-30 3-16 halfword and signed data transfer with register offset ................................ ........ 3-34 3-17 halfword and signed data transfer with immediate offset and auto-indexing ....... 3-35 3-18 block data transfer instructions ................................ ................................ ............. 3-40 3-19 post-increment addressing ................................ ................................ ..................... 3-41 3-20 pre-increment addressing ................................ ................................ ...................... 3-42 3-21 post-decrement addressing ................................ ................................ ................... 3-42 3-22 pre-decrement addressing ................................ ................................ ..................... 3-43 3-23 swap instruction ................................ ................................ ................................ ..... 3-47 3-24 software interrupt instruction ................................ ................................ .................. 3-49 3-25 coprocessor data operation instruction ................................ ................................ . 3-51 3-26 coprocessor data transfer instructions ................................ ................................ .. 3-53 3-27 coprocessor register transfer instructions ................................ ............................ 3-56 3-28 undefined instruction ................................ ................................ ............................. 3-58 3-29 thumb instruction set formats ................................ ................................ ............. 3-65
xvi S3F441FX risc micro processor list of figures (continued) figure title page number number 3-30 format 1 ................................ ................................ ................................ ................. 3-68 3-31 format 2 ................................ ................................ ................................ ................. 3-70 3-32 format 3 ................................ ................................ ................................ ................. 3-72 3-33 format 4 ................................ ................................ ................................ ................. 3-74 3-34 format 5 ................................ ................................ ................................ ................. 3-76 3-35 format 6 ................................ ................................ ................................ ................. 3-79 3-36 format 7 ................................ ................................ ................................ ................. 3-81 3-37 format 8 ................................ ................................ ................................ ................. 3-83 3-38 format 9 ................................ ................................ ................................ ................. 3-85 3-39 format 10 ................................ ................................ ................................ ............... 3-87 3-40 format 11 ................................ ................................ ................................ ............... 3-89 3-41 format 12 ................................ ................................ ................................ ............... 3-90 3-42 format 13 ................................ ................................ ................................ ............... 3-92 3-43 format 14 ................................ ................................ ................................ ............... 3-93 3-44 format 15 ................................ ................................ ................................ ............... 3-95 3-45 f ormat 16 ................................ ................................ ................................ ............... 3-96 3-46 format 17 ................................ ................................ ................................ ............... 3-98 3-47 format 18 ................................ ................................ ................................ ............... 3-99 3-48 format 19 ................................ ................................ ................................ ............... 3-100 4-1 S3F441FX memory map after reset ................................ ................................ ....... 4-2 4-2 S3F441FX nwait(16bit bus width) work-around timing diagram ......................... 4-5 4-3 S3F441FX nxbreq/nxback timing diagram ................................ ...................... 4-7 4-4 memory interface with 8bit rom ................................ ................................ ............ 4-8 4-5 memory interface with 8bit rom x 2 ................................ ................................ ....... 4-8 4-6 memory interface with 8bit rom x 4 ................................ ................................ ....... 4-9 4-7 memory interface with 16bit rom ................................ ................................ .......... 4-10 4-8 memory interface with 16bit sram ................................ ................................ ........ 4-10 4-9 memory interface with 16bit dram ................................ ................................ ........ 4-11 4-10 memory interface with 16bit dram x 2 ................................ ................................ ... 4-11 4-11 memory interface with 16bit sdram ................................ ................................ ...... 4-12 4-12 S3F441FX ngcs timing diagram ................................ ................................ .......... 4-13 4-13 S3F441FX dram timing diagram ................................ ................................ ......... 4-14 4-14 S3F441FX dram refresh timing diagram ................................ ............................ 4-14 4-15 S3F441FX sdram timing diagram ................................ ................................ ....... 4-15 5-1 watchdog timer block diagram ................................ ................................ ............. 5-1
S3F441FX risc microprocessor xvii list of figures (continued) figure title page number number 6-1 16-bit timer block diagram ................................ ................................ ................... 6-2 6-2 interval mode example 1 (tndata=100, tnpre=3, utclk is a timer source) .... 6-3 6-3 interval mode example 2 (tndata=100, tin is a timer source ) ............................ 6-4 6-4 t imer 0,1,2,3,4,5 control registers ................................ ................................ ........ 6-6 6-5 timer data registers (tndata) ................................ ................................ ............. 6-7 6-6 timer count registers (tncnt) ................................ ................................ ............. 6-8 6-7 timer pre-scaler registers (tnpre) ................................ ................................ ..... 6-9 7-1 uart block diagram ................................ ................................ ............................. 7-2 7-2 infra-red mode ................................ ................................ ................................ ........ 7-3 7-3 uart line control register (lcon) ................................ ................................ ...... 7-5 7-4 uart control register (ucon) ................................ ................................ ............. 7-7 7-5 uart status register (ussr) ................................ ................................ ............... 7-9 7-6 uart transmit buffer register (tbr) ................................ ................................ .... 7-10 7-7 uart receive buffer register (rbr) ................................ ................................ .... 7-11 7-8 uart baud rate divisor registers (ubrdr) ................................ ........................ 7-12 8-1 S3F441FX interrupt structure ................................ ................................ ................. 8-2 9-1 s3f44 1fx default memory map of the normal mode(in rom mode) .................... 9-2 9-2 S3F441FX default memory map of external rom mode ................................ ........ 9-3 9-3 system register address configuration register (syscfg) ................................ .. 9-4 9-4 an example of S3F441FX ncsn timing diagram ................................ .................. 9-6 10-1 flash memory read/write block diagram ................................ .............................. 10-3 10-2 normal sector program flowchart in a user program mode (in the figure: ? ? compare end address) ................................ ............................... 10-8 10-3 option sector program flowchart in a user program mode ................................ ... 10-8 10-4 normal sector erase flowchart ................................ ................................ .............. 10-9 10-5 option sector erase flowchart ................................ ................................ ............... 10-9 10-6 flash memory map according to operating mode ................................ .................. 10-13 11-1 clock circuit diagram ................................ ................................ ............................ 11-1 11-2 entering & wake-up in the stop mode ................................ ................................ . 11-2 11-3 pll (phase-locked loop) block diagram ................................ .............................. 11-4 11-4 capacitor for pll loop filter ................................ ................................ .................. 11-5 12-1 S3F441FX default memory map of the normal mode (in-rom mode) ................... 12-1 12-2 special function register ................................ ................................ ....................... 12-1
xviii S3F441FX risc micro processor list of figures (concluded) figure title page number number 13-1 typical operating frequency and voltage range ( internal flash t acc =1 ) ............... 13-3 13-2 typical o perating frequency and voltage range ( internal flash t acc =2 ) ............... 13-3 13-3 extclk and mclk (internal clock) when pll is not used. ................................ .. 13-5 13-4 sram read access timing without nwait (t cos =1, t acs =0, t coh =0, t acc =3) ................................ ................................ ........... 13-6 13-5 sram read access timing with nwait (t cos =1, t acs =0, t coh =0, t acc =3, external wait=2) ................................ ................. 13-6 13-6 sram write access timing without nwait (t cos =1, t acs =0, t coh =0, t acc =3) ................................ ................................ ........... 13-7 13-7 sram write access timing with nwait (t cos =1, t acs =0, t coh =0, t acc =3, external wait=2) ................................ ................. 13-7 13-8 sram read ac cess timing with nwait (t cos =0, t acs =1, t coh =1,t acc =3, external wait=2) ................................ .................. 13-8 13-9 sram read access timing with nwait at the last cycle of half-word/word access and byte access (t cos =0, t acs =1, t coh =0,t acc =3, external wait=2) ................................ .................. 13-8 13-10 sram read access timing with nwait during half-word/word access and byte access, except the last cycle (t cos =0, t acs =1, t coh =0,t acc =3, external wait=2) ................................ .................. 13-9 13-11 nwait data fetch timing ................................ ................................ ...................... 13-9 14-1 64-lqfp-1010 package dimensions (unit: mm) ................................ ..................... 14-1
S3F441FX risc microprocessor xix list of tables table title page number number 1-1 S3F441FX signal descriptions (64-pin lqfp) ................................ ........................ 1-5 1-2 S3F441FX i/o pin types ................................ ................................ ........................ 1-7 2-1 psr mode bit values ................................ ................................ ............................. 2-9 2-2 exception entry/exit ................................ ................................ ............................... 2-11 2-3 exception vectors ................................ ................................ ................................ .. 2-13 3-1 the arm instruction set ................................ ................................ ........................ 3-2 3-2 condition code summary ................................ ................................ ...................... 3-4 3-3 arm data processing instructions ................................ ................................ .......... 3-11 3-4 incremental cycle times ................................ ................................ ........................ 3-16 3-5 assembler syntax descriptions ................................ ................................ .............. 3-27 3-6 addressing mode names ................................ ................................ ........................ 3-45 3-7 thumb instruction set opcodes ................................ ................................ ............ 3-66 3-8 summary of format 1 instructions ................................ ................................ .......... 3-68 3-9 summary of format 2 instructions ................................ ................................ .......... 3-70 3-10 summary of format 3 instructions ................................ ................................ .......... 3-72 3-11 summary of format 4 instructions ................................ ................................ .......... 3-74 3-12 summary of format 5 instructions ................................ ................................ .......... 3-76 3-13 summary of pc-relative load instruction ................................ .............................. 3-79 3-14 summary of format 7 instructions ................................ ................................ .......... 3-82 3-15 summary of format 8 instructions ................................ ................................ ........... 3-83 3-16 summary of format 9 instructions ................................ ................................ .......... 3-85 3-17 halfword data transfer instructions ................................ ................................ ........ 3-87 3-18 sp-relative load/store instructions ................................ ................................ ....... 3-89 3-19 load address ................................ ................................ ................................ ......... 3-90 3-20 the add sp instruction ................................ ................................ ......................... 3-92 3-21 push and pop instructions ................................ ................................ ................... 3-93 3-22 the multiple load/store instructions ................................ ................................ ....... 3-95 3-23 the conditional branch instructions ................................ ................................ ....... 3-96 3-24 the swi instruction ................................ ................................ ................................ 3-98 3-25 summary of branch instruction ................................ ................................ .............. 3-99 3-26 the bl instruction ................................ ................................ ................................ .. 3-101 5-1 basic timer counter setting (at extclk = 20 mhz) ................................ .............. 5-2 5-2 the delay time before cpu time start (at extclk = 20 mhz) ............................ 5-2 5-3 watch dog timer counter setting (at 20 mhz) ................................ ...................... 5-2
xx S3F441FX risc micro processor list of tables (concluded) table title page number number 8-1 S3F441FX port configuration overview ................................ ................................ . 8-2 8-2 port of group a control regis ters (pcona,pdata,pupa) ................................ ... 8-6 8-3 port of group b control registers (pconb,pdatb) ................................ .............. 8-8 8-4 port of group c control registers (pconc,pdatc,pupc) ................................ ... 8-9 8-5 port of group d control registers (pcond, pdatd, pupd) ................................ . 8-10 8-6 port of group e control registers (pcone, pdate) ................................ ............. 8-11 8-7 port of group f control registers (pconf, pdatf, pupf) ................................ .. 8-12 8-8 port of group g control registers (pcong, pdatg, pupg) ................................ 8-13 8-9 external interrupt control register (extint) ................................ .......................... 8-15 8-10 d[15:0] pull-up control register (pups) ................................ ................................ 8-16 10-1 the pin s used to read/write/erase the flash rom in tool program mode ........... 10-14 12-1 S3F441FX special registers ................................ ................................ .................. 12-2 13-1 absolute maximum ratings ................................ ................................ .................... 13-1 13-2 d.c. electrical characteristics ................................ ................................ ................ 13-2 13-3 typical quiescent supply current on v dd @ normal mode, flash tacc=1 ............ 13-4 13-4 typical quiescent supply current on v dd @ normal mode, flash tacc=2 ............ 13-4 13-5 typical quiescent supply current on v dd @ idle mode ................................ ......... 13-4 13-6 timing constants ................................ ................................ ................................ ... 13-10 13-7 ac electrical characteristics for internal flash rom ................................ .............. 13-10
S3F441FX risc microprocessor xxi list of instruction descriptions instruction full instruction name page mnemonic number move shifted ................................ ................................ ................................ ................................ ............... 3-68 add/subtract ................................ ................................ ................................ ................................ ................ 3-70 move/compare/add/subtract immediate ................................ ................................ ................................ ..... 3-72 alu operations ................................ ................................ ................................ ................................ ........... 3-74 hi-register operations/branch exchange ................................ ................................ ................................ .... 3-76 pc-relative load ................................ ................................ ................................ ................................ ........ 3-79 load/store with register offset ................................ ................................ ................................ ................... 3-81 load/store sign-extended byte/halfword ................................ ................................ ................................ .... 3-83 load/store with immediate offset ................................ ................................ ................................ ............... 3-85 load/store halfword ................................ ................................ ................................ ................................ .... 3-87 sp-relative load/store ................................ ................................ ................................ ............................... 3-89 load address ................................ ................................ ................................ ................................ ............... 3-90 add offset to stack pointer ................................ ................................ ................................ .......................... 3-92 push/pop registers ................................ ................................ ................................ ................................ ..... 3-93 multiple load/store ................................ ................................ ................................ ................................ ...... 3 -95 conditional branch ................................ ................................ ................................ ................................ ...... 3-96 software interrupt ................................ ................................ ................................ ................................ ........ 3-98 unconditional branch ................................ ................................ ................................ ................................ ... 3-99 long branch with link ................................ ................................ ................................ ................................ . 3-100
S3F441FX risc microcontroller product o verview 1- 1 1 product overview introduction samsung S3F441FX 16/32-bit risc micro-controller is a cost -effective and high-performance solution for hdd and general purpose applications. an outstanding feature of the S3F441FX is its cpu core, a 16/32-bit risc processor (arm7tdmi) designed by advanced risc machines, ltd. the arm7tdmi core is a low-power, general-purpose, microprocessor macro- cell which was developed for the use in application-specific and customer-specific integrated circuits. its simple, elegant, and fully static design is particularly suitable for cost-sensitive and power-sensitive applications. the S3F441FX has been developed by using the arm7tdmi core, cmos standard cell, and data path compiler. most of the on-chip function blocks have been designed by using a hdl synthesizer. the S3F441FX has been fully verified in samsung asic test environment including internal qualification assurance process. by providing a complete set of common system peripherals, the S3F441FX can minimize the overall system costs and eliminate the need to configure additional components, externally. the integrated on-chip functions which are described in this document include: ? memory system manager: 3 external memory banks. (if the internal flash rom is not used for a boot code, ncs0 will be used for a boot rom ) ? built-in 256kbyte (64k x 32bit) flash memory ? 8k-bytes (2k x 32bit) internal sram for stack, data memory, and/or code memory ? one channel uart ? six 16-bit internal timers with 8-bit pre- scaler and input capture function ? power down mode: stop and idle modes ? one 8-bit basic timer and 3-bit watch-dog timer ? interrupt controller (total of 19 interrupt sources including 3 external sources ) ? sixteen programmab le i/o ports ? on-chip pll ? 64-pin lqfp
product overview s3 f441fx risc microcontroller 1- 2 features architecture completely integrated micro-controller for embedded applications, especially hdd application fully 16/32-bit risc architecture efficient and powerful arm7tdmi cpu core cost effective jtag-based debugging solution memory 8 -bit external bus support for one rom bank and two external memory banks programmable memory access times (from 0 to 7 wait cycles) 8-kbyte sram (for stack, data memory, and/or code memory) built-in 256kbyte flash memory (for data and/or code memory ) uart one uart channel with interrupt-based operation programmable baud rates supports asynchronous serial data transmit/receive operations with 5-bit, 6-bit, 7- bit, 8-bit frames 16-bit timers/counters with capture function (t0, t1, t2, t3, t4 and t5) six programmable 16-bit timer/counters interval, capture, or match & overflow mode operations extclk or tin (timer input capture signal) can be the clock source for the timer. tin is shared by all timers. basic timer and watch-dog timer 8-bit counter (basic timer) + 3-bit counter (watch-dog timer). overflow signal from the 8-bit counter can generate a basic timer interrupt and can be the input clock for the 3-bit counter. overflow signal from the 3-bit counter resets the system. i/o ports 16 programmable i/o ports ( 7 dedicated i/o pins only) each port pin can be configured individually as input, output, or functional pin interrupts 19 interrupt sources including 3 exter nal interrupt sources. normal or fast interrupt mode(irq, fiq) power down mode idle and stop modes division of system clock to reduce the power (1/1,1/2, 1/8, 1/16 and 1/1024) programmable pll for system clock the on-chip pll generates the clock for the mcu up to 40 mhz. there is an external capacitor for the pll loop filter. operating voltage range 3.0 to 3.6 v operating frequency range up to 40 mhz package type 64-pin lqfp
S3F441FX risc microcontroller product o verview 1- 3 block diagram i/o port controller system manager sytem bus controller bus arbitration bus interface rom/sram controller uart timer 0,1,2,3,4,5 clock control (power down) basic timer & wdt interrupt controller bus router local bus address/data bus / control signals cpu (arm7tdmi) 8k-byte sram 256 k-byte flash rom pll figure 1-1. S3F441FX block diagram
product overview s3 f441fx risc microcontroller 1- 4 pin assignments S3F441FX (64-lqfp) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v dd a0 a1 a2 a3 a4 a5 v ss a6 a7 a8 a9 a10 a11 vdd a12/gpio8 v ss extclk eint0 eint1 eint2 tin/gpio7 gpio0 v dd gpio1 gpio2 gpio3 gpio4 gpio5 pllcap gpio6 tdo nwe noe ncs0 ncs1 ncs2 nwait v ss d7 d6 d5 d4 v dd d3 d2 d1 d0 a13/gpio9 a14/gpio10 a15/gpio11 nreset a16/gpio12 a17/gpio13 md1 md0 ntrst vss vdd txd/gpio14 rxd/gpio15 tdi tms tck figure 1-2. S3F441FX pin assignments (64-lqfp)
S3F441FX risc microcontroller product o verview 1- 5 signal descriptions table 1-1. S3F441FX signal descriptions (64-pin lqfp) signal pin # i/o pin type description tdo 64 o tdo (tap controller data output) is the serial output for the jtag port tck 1 iu tck (tap controller clock) provides the clock input for the jtag logic. a 100k pull-up resistor is connected to the tck pin internally. tms 2 iu tms (tap controller mode select) controls the sequence of the tap controller state diagram. a 100k pull-up resistor is connected to the tms pin internally. tdi 3 iu tdi (tap controller data input) is the serial input for the jtag port. a 100k pull-up resister is connected to the tdi pin internally. ntrst 8 iu ntrst(tap controller reset) resets the tap controller at start. a 100k pull-up resistor is connected to the ntrst pin internally. if the debugger(black ice) is not used, ntrst pin should be l level or low active pulse should be applied before running the cpu. for example, nreset signal can be tied with the ntrst. md[1:0] 10,9 i 00: normal mode(in-rom mode). the ncs0 may be used for an external device. (mds can be used.) 01: external rom mode. the ncs0 will be used for boot code instead of the internal flash rom. (mds can be used.) 10: optional mds mode for ice. (external rom mode is selected) 11: test mode for internal flash memory, which is used only a flash writer equipment. nreset 13 ius nreset is the global reset input for the S3F441FX. for a safe system reset, nreset should be held at low level for at least 150us. a17/gpio13 11 iopd a17: address line a17 gpio[13]: programmable i/o port 13 for push-pull input or output. a16/gpio12 12 iopd a16: address line a16 gpio[12]: programmable i/o port 12 for push-pull input or output. a15/gpio11 14 iopd a15: address line a15 gpio[11]: programmable i/o port 11 for push-pull input or output. a14/gpio10 15 iopd a14: address line a14 gpio[10]: programmable i/o port 10 for push-pull input or output. a13/gpio9 16 iopd a13: address line a13 gpio[9]: programmable i/o port 9 for push-pull input or output. a12/gpio8 17 iopd a12: address line a12 gpio[8]: programmable i/o port 8 for push-pull input or output. a[11:0] 19-24, 26-31 o address lines a11-a0
product overview s3 f441fx risc microcontroller 1- 6 table 1-1. S3F441FX signal descriptions (64-pin lqfp) (continued) signal pin # i/o pin type description nwe 33 o nwe (write enable) indicates that the current bus cycle is a write cycle. noe 34 o noe (output enable) indicates that the current bus cycle is a read cycle. nwait 38 iu nwait requests to prolong a current bus cycle. as long as nwait is l, the current bus cycle cannot be completed. ncs0 35 o ncs0 (chip select 0) can be activated when the issued address for memory access is within the address region 0x0-0x3ffff and md[1:0] is configured as an external rom mode. ncs1 36 o ncs1(chip select 1) can be activated when the issued address for memory access is within the address region 0x800000- 0x83ffff. ncs2 37 o ncs2(chip select 2) can be activated when the issued address for memory access is within the address region 0xc00000- 0xc3ffff. d[7:0] 40-43, 45-48 iopd d[7:0] (bi-directional data bus) inputs data during memory read and outputs data during memory write. extclk 50 is external clock source. extclk can be fed to the pll and the timers eint[2:0] 53-51 iopuse external interrupt inputs2-0. tin/gpio7 54 iopus tin: timer capture input gpio[7]: programmable i/o port 7 for push-pull input or output. gpio[6:0] 63,61- 57,55 iopu gpio[6:0]: programmable i/o port 6~0 for push-pull input/output. rxd/gpio15 4 iopus rxd: rx data input for the uart gpio[15]: programmable i/o port 15 for push-pull input or output. txd/gpio14 5 iopus txd: tx data output for the uart gpio[14]: programmable i/o port 14 for push-pull input or output. pllcap 62 a loop filter capacitor for the system pll. ( 700pf ) v dd 6,18,32, 44,56 - v dd ( 3.3 v ) v ss 7,25,39, 49 - v ss
S3F441FX risc microcontroller product o verview 1- 7 i/o pin types table 1-2. S3F441FX i/o pin types i/o type descriptios iopus schmitt-trigger input/output pin with programmable pull-up resistor iopuse schmitt-trigger input/output pin with programmable pull-up resistor and edge detection iopd input/output pin with programmable pull-down resistor iopu input/output pin with programmable pull-up resistor o output pin ius schmitt-trigger input pin with pull-up resistor i input pin iu input pin with pull-up resistor is schmitt-trigger input pin a a pin for analog signal
product overview s3 f441fx risc microcontroller 1- 8 pull-up resistor (typical 50 k w ) v dd i/o v dd output data pull-up enable v ss input data external interrupt input output enable figure 1-3. iopuse ( schmitt input/output pin with programmable pull-up resistor and edge detection) pull-up resistor (typical 50 k w ) v dd i/o v dd output data pull-up enable v ss input data output enable figure 1-4. iopus ( schmitt input/output pin with programmable pull-up resistor)
S3F441FX risc microcontroller product o verview 1- 9 pull-up resistor (typical 50 k w ) v dd i/o output data v ss input data output enable power-down enable v ss figure 1-5. iopd ( input/output pin with programmable pull-down resistor) pull-up resistor (typical 50 k w ) v dd i/o v dd output data pull-up enable v ss input data output enable figure 1-6. iopu ( input/output pin with programmable pull-up resistor)
S3F441FX risc microcontroller programme r's model 2- 1 2 programmer's model overview S3F441FX was developed using the advanced arm7tdmi core designed by advanced risc machines, ltd. processor operating states from the programmer's point of view, the arm7tdmi can be in one of two states: ? arm state which executes 32-bit, word-aligned arm instructions. ? thumb state which operates with 16-bit, half-word-aligned thumb instructions. in this state, the pc uses bit 1 to select between alternate half-words. note transition between these two states does not affect the processor mode or the contents of the registers. switching state entering thumb state entry into thumb state can be achieved by executing a bx instruction with the state bit (bit 0) set in the operand register. transition to thumb state will also occur automatically on return from an exception (irq, fiq, undef, abort, swi etc.), if the exception was entered with the processor in thumb state. entering arm state entry into arm state happens: ? on execution of the bx instruction with the state bit clear in the operand register. ? on the processor taking an exception (irq, fiq, reset, undef, abort, swi etc.). in this case, the pc is placed in the exception mode's link register, and execution commences at the exception's vector address. memory formats arm7tdmi views memory as a linear collection of bytes numbered upwards from zero. bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second and so on. arm7tdmi can treat words in memory as being stored either in big- endian or little- endian format.
programmer's model S3F441FX risc micro controller 2- 2 big-endian format in big- endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. byte 0 of the memory system is therefore connected to data lines 31 through 24. 31 8 4 0 23 9 5 1 10 6 2 11 7 3 8 7 0 4 0 8 higher address lower address word address most significant byte is at lowest address. word is addressed by byte address of most significant byte. 24 15 16 figure 2-1. big- endian addresses of bytes within words little-endian format in little- endian format, the lowest numbered byte in a word is considered the word's least significant byte, and the highest numbered byte the most significant. byte 0 of the memory system is therefore connected to data lines 7 through 0. 31 23 8 7 0 4 0 8 higher address lower address word address least significant byte is at lowest address. word is addressed by byte address of least significant byte. 24 15 16 8 4 0 9 5 1 10 6 2 11 7 3 figure 2-2. little- endian addresses of bytes within words instruction length instructions are either 32 bits long (in arm state) or 16 bits long (in thumb state). data types arm7tdmi supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. words must be aligned to four- byte boundaries and half words to two-byte boundaries.
S3F441FX risc microcontroller programme r's model 2- 3 operating modes arm7tdmi supports seven modes of operation: ? user (usr): the normal arm program execution state ? fiq ( fiq): designed to support a data transfer or channel process ? irq ( irq): used for general-purpose interrupt handling ? supervisor ( svc): protected mode for the operating system ? abort mode ( abt): entered after a data or instruction pre-fetch abort ? system (sys): a privileged user mode for the operating system ? undefined ( und): entered when an undefined instruction is executed mode changes may be made under software control, or may be brought about by external interrupts or exception processing. most application programs will execute in user mode. the non-user modes' known as privileged modes-are entered in order to service interrupts or exceptions, or to access protected resources. registers arm7tdmi has a total of 37 registers - 31 general-purpose 32-bit registers and six status registers - but these cannot all be seen at once. the processor state and operating mode dictate which registers are available to the programmer. the arm state register set in arm state, 16 general registers and one or two status registers are visible at any one time. in privileged (non- user) modes, mode-specific banked registers are switched in. figure 2-3 shows which registers are available in each mode: the banked registers are marked with a shaded triangle. the arm state register set contains 16 directly accessible registers: r0 to r15. all of these except r15 are general-purpose, and may be used to hold either data or address values. in addition to these, there is a seventeenth register used to store status information. register 14 is used as the subroutine link register. this receives a copy of r15 when a branch and link (bl) instruction is executed. at all other times it may be treated as a general- purpose register. the corresponding banked registers r14_svc, r14_irq, r14_fiq, r14_abt and r14_und are similarly used to hold the return values of r15 when interrupts and exceptions arise, or when branch and link instructions are executed within interrupt or exception routines. register 15 holds the program counter (pc). in arm state, bits [1:0] of r15 are zero and bits [31:2] contain the pc. in thumb state, bit [0] is zero and bits [31:1] contain the pc. register 16 is the cpsr (current program status register). this contains condition code flags and the current mode bits. fiq mode has seven banked registers mapped to r8-14 (r8_fiq-r14_fiq). in arm state, many fiq handlers do not need to save any registers. user, irq, supervisor, abort and undefined each have two banked registers mapped to r13 and r14, allowing each of these modes to have a private stack pointer and link registers.
programmer's model S3F441FX risc micro controller 2- 4 r0 r1 r2 r3 r4 r5 r6 r7 r9 r8 r10 r11 r12 r13 r14 r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r9 r8 r10 r11 r12 r13_ svc r14_ svc r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r9_ fiq r10_ fiq r11_ fiq r12_ fiq r13_ fiq r14_ fiq r15 (pc) r8_ fiq r0 r1 r2 r3 r4 r5 r6 r7 r9 r8 r10 r11 r12 r13_ abt r14_ abt r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r9 r8 r10 r11 r12 r13_ irq r14_ irq r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r9 r8 r10 r11 r12 r13_ und r14_ und r15 (pc) system & user fiq supervisor irq abort undefined arm state general registers and program counter arm state program status registers cpsr cpsr spsr_ fiq cpsr spsr_ irq = banked register cpsr spsr_ und cpsr spsr_ abt cpsr spsr_ svc figure 2-3. register organization in arm state
S3F441FX risc microcontroller programme r's model 2- 5 the thumb state register set the thumb state register set is a subset of the arm state set. the programmer has direct access to eight general registers, r0-r7, as well as the program counter (pc), a stack pointer register (sp), a link register (lr), and the cpsr. there are banked stack pointers, link registers and saved process status registers ( spsrs) for each privileged mode. this is shown in figure 2-4. r0 r1 r2 r3 r4 r5 r6 r7 lr sp pc system & user fiq supervisor irq abort undefined thumb state general registers and program counter thumb state program status registers cpsr cpsr spsr_ fiq cpsr spsr_ svc cpsr spsr_ abt cpsr spsr_ irq cpsr spsr_ und = banked register lr_ fiq r0 r1 r2 r3 r4 r5 r6 r7 sp_ fiq pc lr_ svc r0 r1 r2 r3 r4 r5 r6 r7 sp_ svc pc lr_ und r0 r1 r2 r3 r4 r5 r6 r7 sp_ und pc lr_ fiq r0 r1 r2 r3 r4 r5 r6 r7 sp_ fiq pc lr_ abt r0 r1 r2 r3 r4 r5 r6 r7 sp_ ab t pc figure 2-4. register organization in thumb state
programmer's model S3F441FX risc micro controller 2- 6 the relationship between arm and thumb state registers the thumb state registers relate to the arm state registers in the following way: ? thumb state r0-r7 and arm state r0-r7 are identical ? thumb state cpsr and spsrs and arm state cpsr and spsrs are identical ? thumb state sp maps onto arm state r13 ? thumb state lr maps onto arm state r14 ? the thumb state program counter maps onto the arm state program counter (r15) this relationship is shown in figure 2-5. r0 r1 r2 r3 r4 r5 r6 r7 stack pointer (sp) link register (lr) program counter (pc) cpsr spsr r0 r1 r2 r3 r4 r5 r6 r7 r9 r8 r10 r11 r12 stack pointer (r13) link register (r14) program counter (r15) cpsr spsr lo-registers hi-registers thumb state arm state figure 2-5. mapping of thumb state registers onto arm state registers
S3F441FX risc microcontroller programme r's model 2- 7 accessing hi-registers in thumb state in thumb state, registers r8-r15 (the hi registers) are not part of the standard register set. however, the assembly language programmer has limited access to them, and can use them for fast temporary storage. a value may be transferred from a register in the range r0-r7 (a lo register) to a hi register, and from a hi register to a lo register, using special variants of the mov instruction. hi register values can also be compared against or added to lo register values with the cmp and add instructions. for more information, refer to figure 3-34. the program status registers the arm7tdmi contains a current program status register (cpsr), plus five saved program status registers ( spsrs) for use by exception handlers. these register's functions are: ? hold information about the most recently performed a lu operation ? control the enabling and disabling of interrupts ? set the processor operating mode the arrangement of bits is shown in figure 2-6. 31 condition code flags overflow n z c v i f t m4 m3 m2 m1 m0 30 29 27 28 26 25 24 23 8 7 6 5 4 3 2 1 0 (reserved) control bits carry/borrow/extend zero negative/less than mode bits state bit fiq disable irq disable ~ ~ ~ ~ figure 2-6. program status register format
programmer's model S3F441FX risc micro controller 2- 8 the condition code flags the n, z, c and v bits are the condition code flags. these may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed. in arm state, all instructions may be executed conditionally: see table 3-2 for details. in thumb state, only the branch instruction is capable of conditional execution: see figure 3-46 for details. the control bits the bottom 8 bits of a psr (incorporating i, f, t and m[4:0]) are known collectively as the control bits. these will be changed when an exception arises. if the processor is operating in a privileged mode, they can also be manipulated by software. the t bit this reflects the operating state. when this bit is set, the processor is executing in thumb state, otherwise it is executing in arm state. this is reflected on the tbit external signal. note that the software must never change the state of the tbit in the cpsr. if this happens, the processor will enter an unpredictable state. interrupt disable bits the i and f bits are the interrupt disable bits. when set, these disable the irq and fiq interrupts respectively. the mode bits the m4, m3, m2, m1 and m0 bits (m[4:0]) are the mode bits. these determine the processor's operating mode, as shown in table 2-1. not all combinations of the mode bits define a valid processor mode. only those explicitly described shall be used. the user should be aware that if any illegal value is programmed into the mode bits, m[4:0], then the processor will enter an unrecoverable state. if this occurs, reset should be applied. reserved bits the remaining bits in the psrs are reserved. when changing a psr's flag or control bits, you must ensure that these unused bits are not altered. also, your program should not rely on them containing specific values, since in future processors they may read as one or zero.
S3F441FX risc microcontroller programme r's model 2- 9 table 2-1. psr mode bit values m[4:0] mode visible thumb state registers visible arm state registers 10000 user r7..r0, lr, sp pc, cpsr r14..r0, pc, cpsr 10001 fiq r7..r0, lr_fiq, sp_fiq pc, cpsr, spsr_fiq r7..r0, r14_fiq..r8_fiq, pc, cpsr, spsr_fiq 10010 irq r7..r0, lr_irq, sp_irq pc, cpsr, spsr_irq r12..r0, r14_irq, r13_irq, pc, cpsr, spsr_irq 10011 supervisor r7..r0, lr_svc, sp_svc, pc, cpsr, spsr_svc r12..r0, r14_svc, r13_svc, pc, cpsr, spsr_svc 10111 abort r7..r0, lr_abt, sp_abt, pc, cpsr, spsr_abt r12..r0, r14_abt, r13_abt, pc, cpsr, spsr_abt 11011 undefined r7..r0 lr_und, sp_und, pc, cpsr, spsr_und r12..r0, r14_und, r13_und, pc, cpsr 11111 system r7..r0, lr, sp pc, cpsr r14..r0, pc, cpsr reserved bits the remaining bits in the psr's are reserved. when changing a psr's flag or control bits, you must ensure that these unused bits are not altered. also, your program should not rely on them containing specific values, since in future processors they may read as one or zero.
programmer's model S3F441FX risc micro controller 2- 10 exceptions exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished. it is possible for several exceptions to arise at the same time. if this happens, they are dealt with in a fixed order. see exception priorities on page 2-14. action on entering an exception when handling an exception, the arm7tdmi: 1. preserves the address of the next instruction in the appropriate link register. if the exception has been entered from arm state, then the address of the next instruction is copied into the link register (that is, current pc + 4 or pc + 8 depending on the exception. see table 2-2 on for details). if the exception has been entered from thumb state, then the value written into the link register is the current pc offset by a value such that the program resumes from the correct place on return from the exception. this means that the exception handler need not determine which state the exception was entered from. for example, in the case of swi, movs pc, r14_svc will always return to the next instruction regardless of whether the swi was executed in arm or thumb state. 2. copies the cpsr into the appropriate spsr 3. forces the cpsr mode bits to a value which depends on the exception 4. forces the pc to fetch the next instruction from the relevant exception vector it may also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. if the processor is in thumb state when an exception occurs, it will automatically switch into arm state when the pc is loaded with the exception vector address. action on leaving an exception on completion, the exception handler: 1. moves the link register, minus an offset where appropriate, to the pc. (the offset will vary depending on the type of exception.) 2. copies the spsr back to the cpsr 3. clears the interrupt disable flags, if they were set on entry note an explicit switch back to thumb state is never needed, since restoring the cpsr from the spsr automatically sets the t bit to the value it held immediately prior to the exception.
S3F441FX risc microcontroller programme r's model 2- 11 exception entry/exit summary table 2-2 summarizes the pc value preserved in the relevant r14 on exception entry, and the recommended instruction for exiting the exception handler. table 2-2. exception entry/exit return instruction previous state notes arm r14_x thumb r14_x bl mov pc, r14 pc + 4 pc + 2 1 swi movs pc, r14_svc pc + 4 pc + 2 1 udef movs pc, r14_und pc + 4 pc + 2 1 fiq subs pc, r14_fiq, #4 pc + 4 pc + 4 2 irq subs pc, r14_irq, #4 pc + 4 pc + 4 2 pabt subs pc, r14_abt, #4 pc + 4 pc + 4 1 dabt subs pc, r14_abt, #8 pc + 8 pc + 8 3 reset na ? ? 4 notes: 1. where pc is the address of the bl/swi/undefined instruction fetch which had the prefetch abort. 2. where pc is the address of the instruction which did not get executed since the fiq or irq took priority. 3. where pc is the address of the load or store instruction which generated the data abort. 4. the value saved in r14_svc upon reset is unpredictable. fiq the fiq (fast interrupt request) exception is designed to support a data transfer or channel process, and in arm state has sufficient private registers to remove the need for register saving (thus minimizing the overhead of context switching). fiq is externally generated by taking the nfiq input low. this input can except either synchronous or asynchronous transitions, depending on the state of the isync input signal. when isync is low, nfiq and nirq are considered asynchronous, and a cycle delay for synchronization is incurred before the interrupt can affect the processor flow. irrespective of whether the exception was entered from arm or thumb state, a fiq handler should leave the interrupt by executing subs pc,r14_fiq,#4 fiq may be disabled by setting the cpsr's f flag (but note that this is not possible from user mode). if the f flag is clear, arm7tdmi checks for a low level on the output of the fiq synchroniser at the end of each instruction.
programmer's model S3F441FX risc micro controller 2- 12 irq the irq (interrupt request) exception is a normal interrupt caused by a low level on the nirq input. irq has a lower priority than fiq and is masked out when a fiq sequence is entered. it may be disabled at any time by setting the i bit in the cpsr, though this can only be done from a privileged (non-user) mode. irrespective of whether the exception was entered from arm or thumb state, an irq handler should return from the interrupt by executing subs pc,r14_irq,#4 abort an abort indicates that the current memory access cannot be completed. it can be signalled by the external abort input. arm7tdmi checks for the abort exception during memory access cycles. there are two types of abort: ? prefetch abort: occurs during an instruction prefetch. ? data abort: occurs during a data access. if a prefetch abort occurs, the prefetched instruction is marked as invalid, but the exception will not be taken until the instruction reaches the head of the pipeline. if the instruction is not executed - for example because a branch occurs while it is in the pipeline - the abort does not take place. if a data abort occurs, the action taken depends on the instruction type: ? single data transfer instructions (ldr, str) write back modified base registers: the abort handler must be aware of this. ? the swap instruction (swp) is aborted as though it had not been executed. ? block data transfer instructions (ldm, stm) complete. if write-back is set, the base is updated. if the instruction would have overwritten the base with data ( ie it has the base in the transfer list), the overwriting is prevented. all register overwriting is prevented after an abort is indicated, which means in particular that r15 (always the last register to be transferred) is preserved in an aborted ldm instruction. the abort mechanism allows the implementation of a demand paged virtual memory system. in such a system the processor is allowed to generate arbitrary addresses. when the data at an address is unavailable, the memory management unit (mmu) signals an abort. the abort handler must then work out the cause of the abort, make the requested data available, and retry the aborted instruction. the application program needs no knowledge of the amount of memory available to it, nor is its state in any way affected by the abort. after fixing the reason for the abort, the handler should execute the following irrespective of the state (arm or thumb): subs pc,r14_abt,#4 ; for a prefetch abort, or subs pc,r14_abt,#8 ; for a data abort this restores both the pc and the cpsr, and retries the aborted instruction.
S3F441FX risc microcontroller programme r's model 2- 13 software interrupt the software interrupt instruction (swi) is used for entering supervisor mode, usually to request a particular supervisor function. a swi handler should return by executing the following irrespective of the state (arm or thumb): mov pc,r14_svc this restores the pc and cpsr, and returns to the instruction following the swi. note nfiq, nirq, isync, lock, bigend, and abort pins exist only in the arm7tdmi cpu core. undefined instruction when arm7tdmi comes across an instruction which it cannot handle, it takes the undefined instruction trap. this mechanism may be used to extend either the thumb or arm instruction set by software emulation. after emulating the failed instruction, the trap handler should execute the following irrespective of the state (arm or thumb): movs pc,r14_und this restores the cpsr and returns to the instruction following the undefined instruction. exception vectors the following table shows the exception vector addresses. table 2-3. exception vectors address exception mode in entry 0x00000000 reset supervisor 0x00000004 undefined instruction undefined 0x00000008 software interrupt supervisor 0x0000000c abort ( prefetch) abort 0x00000010 abort (data) abort 0x00000014 reserved reserved 0x00000018 irq irq 0x0000001c fiq fiq
programmer's model S3F441FX risc micro controller 2- 14 exception priorities when multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: highest priority: 1. reset 2. data abort 3. fiq 4. irq 5. prefetch abort lowest priority: 6. undefined instruction, software interrupt. not all exceptions can occur at once: undefined instruction and software interrupt are mutually exclusive, since they each correspond to particular (non-overlapping) decoding of the current instruction. if a data abort occurs at the same time as a fiq, and fiqs are enabled ( ie the cpsr's f flag is clear), arm7tdmi enters the data abort handler and then immediately proceeds to the fiq vector. a normal return from fiq will cause the data abort handler to resume execution. placing data abort at a higher priority than fiq is necessary to ensure that the transfer error does not escape detection. the time for this exception entry should be added to worst-case fiq latency calculations.
S3F441FX risc microcontroller programme r's model 2- 15 interrupt latencies the worst case latency for fiq, assuming that it is enabled, consists of the longest time the request can take to pass through the synchroniser ( tsyncmax if asynchronous), plus the time for the longest instruction to complete ( tldm , the longest instruction is an ldm which loads all the registers including the pc), plus the time for the data abort entry ( texc ), plus the time for fiq entry ( tfiq ). at the end of this time arm7tdmi will be executing the instruction at 0x1c. tsyncmax is 3 processor cycles, tldm is 20 cycles, texc is 3 cycles, and tfiq is 2 cycles. the total time is therefore 28 processor cycles. this is just over 1.4 microseconds in a system which uses a continuous 20 mhz processor clock. the maximum irq latency calculation is similar, but must allow for the fact that fiq has higher priority and could delay entry into the irq handling routine for an arbitrary length of time. the minimum latency for fiq or irq consists of the shortest time the request can take through the synchroniser ( tsyncmin ) plus tfiq . this is 4 processor cycles. reset when the nreset signal goes low, arm7tdmi abandons the executing instruction and then continues to fetch instructions from incrementing word addresses. when nreset goes high again, arm7tdmi: 1. overwrites r14_svc and spsr_svc by copying the current values of the pc and cpsr into them. the value of the saved pc and spsr is not defined. 2. forces m[4:0] to 10011 (supervisor mode), sets the i and f bits in the cpsr, and clears the cpsr's t bit. 3. forces the pc to fetch the next instruction from address 0x00. 4. execution resumes in arm state.
S3F441FX risc microcontroller arm instruction s et 3- 1 3 instruction set instruction set summay this chapter describes the arm instruction set and the thumb instruction set in the arm7tdmi core. format summary the arm instruction set formats are shown below. cond rn data processing/ psr transfer 0 0 i s opcode 0 0 0 p u 0 w l 0 0 0 p u 1 w l 0 1 i p u b w l 0 1 i 1 0 0 p u b w l 1 1 1 1 1 1 1 1 1 0 l 1 1 1 0 p u b w l 1 1 1 1 1 1 0 1 1 1 0 1 l rd rd rn rdhi rdlo rn rn rn rn rd rd rd rn register list rn crn crn crd rd cp opc cp opc operand2 rs rm rm rm rm rn rn rd offset offset crd offset cp# cp# cp# cp cp crm crm ignored by processor 0 1 offset cond cond cond cond cond cond cond cond cond cond cond cond cond cond 0 0 0 0 0 0 a s a s u 1 0 0 0 0 0 0 0 0 0 0 1 b 1 0 0 0 1 0 0 0 1 1 1 1 1 1 0 0 0 0 h h 0 0 0 0 s s 1 1 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 multiply multiply long single data swap branch and exchange halfword data transfer: register offset halfword data transfer: immediate offset single data transfer undefined block data transfer branch coprocessor register transfer coprocessor data operation coprocessor data transfer software interrupt offset 27 26 25 24 23 22 21 20 19 18 17 16 15 13 14 12 11 10 31 30 29 28 9 8 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 19 18 17 16 15 13 14 12 11 10 31 30 29 28 9 8 7 6 5 4 3 2 1 0 figure 3-1. arm instruction set format
arm instruction set S3F441FX risc microcontroller 3- 2 note some instruction codes are not defined but do not cause the undefined instruction trap to be taken, for instance a multiply instruction with bit 6 changed to a 1. these instructions should not be used, as their action may change in future arm implementations. instruction summary table 3-1. the arm instruction set mnemonic instruction action adc add with carry rd: = rn + op2 + carry add add rd: = rn + op2 and and rd: = rn and op2 b branch r15: = address bic bit clear rd: = rn and not op2 bl branch with link r14: = r15, r15: = address bx branch and exchange r15: = rn, t bit: = rn[0] cdp coprocessor data processing (coprocessor-specific) cmn compare negative cpsr flags: = rn + op2 cmp compare cpsr flags: = rn - op2 eor exclusive or rd: = ( rn and not op2) or (op2 and not rn) ldc load coprocessor from memory coprocessor load ldm load multiple registers stack manipulation (pop) ldr load register from memory rd: = (address) mcr move cpu register to coprocessor register crn: = rrn {crm} mla multiply accumulate rd: = ( rm rs) + rn mov move register or constant rd: = op2
S3F441FX risc microcontroller arm instruction s et 3- 3 table 3-1. the arm instruction set (continued) mnemonic instruction action mrc move from coprocessor register to cpu register rd: = crn {crm} mrs move psr status/flags to register rd: = psr msr move register to psr status/flags psr: = rm mul multiply rd: = rm rs mvn move negative register rd: = not op2 orr or rd: = rn or op2 rsb reverse subtract rd: = op2 - rn rsc reverse subtract with carry rd: = op2 - rn - not carry flag sbc subtract with carry rd: = rn - op2 - not carry flag stc store coprocessor register to memory address: = crn stm store multiple stack manipulation (push) str store register to memory

: = rd sub subtract rd: = rn - op2 swi software interrupt os call swp swap register with memory rd: = [ rn], [ rn] := rm teq test bitwise equality cpsr flags: = rn eor op2 tst test bits cpsr flags: = rn and op2
arm instruction set S3F441FX risc microcontroller 3- 4 the condition field in arm state, all instructions are conditionally executed according to the state of the cpsr condition codes and the instruction's condition field. this field (bits 31:28) determines the circumstances under which an instruction is to be executed. if the state of the c, n, z and v flags fulfils the conditions encoded by the field, the instruction is executed, otherwise it is ignored. there are sixteen possible conditions, each represented by a two-character suffix that can be appended to the instruction's mnemonic. for example, a branch (b in assembly language) becomes beq for "branch if equal", which means the branch will only be taken if the z flag is set. in practice, fifteen different conditions may be used: these are listed in table 3-2. the sixteenth (1111) is reserved, and must not be used. in the absence of a suffix, the condition field of most instructions is set to "always" ( sufix al). this means the instruction will always be executed regardless of the cpsr condition codes. table 3-2. condition code summary code suffix flags meaning 0000 eq z set equal 0001 ne z clear not equal 0010 cs c set unsigned higher or same 0011 cc c clear unsigned lower 0100 mi n set negative 0101 pl n clear positive or zero 0110 vs v set overflow 0111 vc v clear no overflow 1000 hi c set and z clear unsigned higher 1001 ls c clear or z set unsigned lower or same 1010 ge n equals v greater or equal 1011 lt n not equal to v less than 1100 gt z clear and (n equals v) greater than 1101 le z set or (n not equal to v) less than or equal 1110 al (ignored) always
S3F441FX risc microcontroller arm instruction s et 3- 5 branch and exchange (bx) this instruction is only executed if the condition is true. the various conditions are defined in table 3-2. this instruction performs a branch by copying the contents of a general register, rn, into the program counter, pc. the branch causes a pipeline flush and refill from the address specified by rn. this instruction also permits the instruction set to be exchanged. when the instruction is executed, the value of rn[0] determines whether the instruction stream will be decoded as arm or thumb instructions. 31 24 27 19 15 8 7 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 cond rn 28 16 11 12 23 20 4 3 [3:0] operand register if bit0 of rn = 1, subsequent instructions decoded as thumb instructions if bit0 of rn =0, subsequent instructions decoded as arm instructions [31:28] condition field figure 3-2. branch and exchange instructions instruction cycle times the bx instruction takes 2s + 1n cycles to execute, where s and n are defined as sequential (s-cycle) and non- sequencial (n-cycle), respectively. assembler syntax bx - branch and exchange. bx { cond} rn { cond} two character condition mnemonic. see table 3-2. rn is an expression evaluating to a valid register number. using r15 as an operand if r15 is used as an operand, the behavior is undefined.
arm instruction set S3F441FX risc microcontroller 3- 6 examples adr r0, into_thumb + 1 ; generate branch target address ; and set bit 0 high - hence ; arrive in thumb state. bx r0 ; branch and change to thumb ; state. code16 ; assemble subsequent code as into_thumb ; thumb instructions adr r5, back_to_arm ; generate branch target t o word aligned address ; - hence bit 0 is low and so change back to arm state. bx r5 ; branch and change back to arm state. align ; word align code32 ; assemble subsequent code as arm instructions back_to_arm
S3F441FX risc microcontroller arm instruction s et 3- 7 branch and branch with link (b, bl) the instruction is only executed if the condition is true. the various conditions are defined table 3-2. the instruction encoding is shown in figure 3-3, below. 31 24 27 cond offset 28 23 [24] link bit 0 = branch 1 = branch with link [31:28] condition field 25 101 l 0 figure 3-3. branch instructions branch instructions contain a signed 2's complement 24 bit offset. this is shifted left two bits, sign extended to 32 bits, and added to the pc. the instruction can therefore specify a branch of +/- 32mbytes. the branch offset must take account of the prefetch operation, which causes the pc to be 2 words (8 bytes) ahead of the current instruction. branches beyond +/- 32mbytes must use an offset or absolute destination which has been previously loaded into a register. in this case the pc should be manually saved in r14 if a branch with link type operation is required. the link bit branch with link (bl) writes the old pc into the link register (r14) of the current bank. the pc value written into r14 is adjusted to allow for the prefetch, and contains the address of the instruction following the branch and link instruction. note that the cpsr is not saved with the pc and r14[1:0] are always cleared. to return from a routine called by branch with link use mov pc,r14 if the link register is still valid or ldm rn!,{..pc} if the link register has been saved onto a stack pointed to by rn. instruction cycle times branch and branch with link instructions take 2s + 1n incremental cycles, where s and n are defined as squential (s-cycle) and internal (i-cycle).
arm instruction set S3F441FX risc microcontroller 3- 8 assembler syntax items in {} are optional. items in <> must be present. b{l}{ cond} { l} used to request the branch with link form of the instruction. if absent, r14 will not be affected by the instruction. { cond} a two-c haracter mnemonic as shown in table 3-2. if absent then al ( always) will be used. the destination. the assembler calculates the offset. examples here bal here ; assembles to 0xeafffffe (note effect of pc offset). b there ; always condition used as default. cmp r1,#0 ; compare r1 with zero and branch to fred ; if r1 was zero, otherwise continue. beq fred ; continue to next instruction. bl sub+rom ; call subroutine at computed address. adds r1,#1 ; add 1 to register 1, setting cpsr flags ; on the result then call subroutine if blcc sub ; the c flag is clear, which will be the ; case unless r1 held 0xffffffff.
S3F441FX risc microcontroller arm instruction s et 3- 9 data processing the data processing instruction is only executed if the condition is true. the conditions are defined in table 3-2. the instruction encoding is shown in figure 3-4. 31 24 27 19 15 cond operand2 28 16 11 12 21 [15:12] destination register [19:16] 1st operand register [20] set condition codes 0 = do not affect condition codes 1 = set condition codes [24:21] operation code 0000 = and-rd: = op1 and op2 0001 = eor-rd: = op1 eor op2 0010 = sub-rd: = op1-op2 0011 = rsb-rd: = op2-op1 0100 = add-rd: = op1+op2 0101 = adc-rd: = op1+op2+c 0110 = sbc-rd: = op1-op2+c-1 0111 = rsc-rd: = op2-op1+c-1 1000 = tst-set condition codes on op1 and op2 1001 = teo-set condition codes on op1 eor op2 1010 = cmp-set condition codes on op1-op2 1011 = smn-set condition codes on op1+op2 1100 = orr-rd: = op1 or op2 1101 = mov-rd: =op2 1110 = bic-rd: = op1 and not op2 1111 = mvn-rd: = not op2 [25] immediate operand 0 = operand 2 is a register 1 = operand 2 is an immediate value [11:0] operand 2 type selection [31:28] condition field 26 25 00 i 20 opcode s rn rd 0 rotate shift rm [3:0] 2nd operand register [11:4] shift applied to rm 4 11 0 3 8 11 0 7 imm [7:0] unsigned 8 bit immediate value [11:8] rotate applied to imm figure 3-4. data processing instructions
arm instruction set S3F441FX risc microcontroller 3- 10 the instruction produces a result by performing a specified arithmetic or logical operation on one or two operands. the first operand is always a register ( rn). the second operand may be a shifted register ( rm) or a rotated 8 bit immediate value ( imm) according to the value of the i bit in the instruction. the condition codes in the cpsr may be preserved or updated as a result of this instruction, according to the value of the s bit in the instruction. certain operations (tst, teq, cmp, cmn) do not write the result to rd. they are used only to perform tests and to set the condition codes on the result and always have the s bit set. the instructions and their effects are listed in table 3-3.
S3F441FX risc microcontroller arm instruction s et 3- 11 cpsr flags the data processing operations may be classified as logical or arithmetic. the logical operations (and, eor, tst, teq, orr, mov, bic, mvn) perform the logical action on all corresponding bits of the operand or operands to produce the result. if the s bit is set (and rd is not r15, see below) the v flag in the cpsr will be unaffected, the c flag will be set to the carry out from the barrel shifter (or preserved when the shift operation is lsl #0), the z flag will be set if and only if the result is all zeros, and the n flag will be set to the logical value of bit 31 of the result. table 3-3. arm data processing instructions assembler mnemonic op code action and 0000 operand1 and operand2 eor 0001 operand1 eor operand2 sub 0010 operand1 - operand2 rsb 0011 operand2 operand1 add 0100 operand1 + operand2 adc 0101 operand1 + operand2 + carry sbc 0110 operand1 - operand2 -not carry flag rsc 0111 operand2 - operand1 not carry flag tst 1000 as and, but result is not written teq 1001 as eor, but result is not written cmp 1010 as sub, but result is not written cmn 1011 as add, but result is not written orr 1100 operand1 or operand2 mov 1101 operand2 (operand1 is ignored) bic 1110 operand1 and not operand2 (bit clear) mvn 1111 not operand2 (operand1 is ignored) the arithmetic operations (sub, rsb, add, adc, sbc, rsc, cmp, cmn) treat each operand as a 32 bit integer (either unsigned or 2's complement signed, the two are equivalent). if the s bit is set (and rd is not r15) the v flag in the cpsr will be set if an overflow occurs into bit 31 of the result; this may be ignored if the operands were considered unsigned, but warns of a possible error if the operands were 2's complement signed. the c flag will be set to the carry out of bit 31 of the alu, the z flag will be set if and only if the result was zero, and the n flag will be set to the value of bit 31 of the result (indicating a negative result if the operands are considered to be 2's complement signed).
arm instruction set S3F441FX risc microcontroller 3- 12 shifts when the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the shift field in the instruction. this field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right). the amount by which the register should be shifted may be contained in an immediate field in the instruction, or in the least-significant byte of another register (other than r15). the encoding for the different shift types is shown in figure 3-5. 0 [6:5] shift type 00 = logical left 01 = logical right 10 = arithmetic right 11 = rotate right [11:7] shift amount 5 bit unsigned integer [6:5] shift type 00 = logical left 01 = logical right 10 = arithmetic right 11 = rotate right [11:8] shift register shift amount specified in the least-significant byte of rs 4 5 6 7 11 1 4 5 6 7 11 8 0 rs figure 3-5. arm shift operations instruction specified shift amount when the shift amount is specified in the instruction, it is contained in a 5 bit field which may take any value from 0 to 31. a logical shift left (lsl) takes the contents of rm and moves each bit by the specified amount to a more significant position. the least significant bits of the result are filled with zeros, and the high bits of rm which do not map into the result are discarded, except that the least significant discarded bit becomes the shifter carry output which may be latched into the c bit of the cpsr when the alu operation is in the logical class (see above). for example, the effect of lsl #5 is shown in figure 3-6. 31 27 26 contents of rm value of operand 2 carry out 0 0 0 0 0 0 figure 3-6. logical shift left note lsl #0 is a special case, where the shifter carry out is the old value of the cpsr c flag. the contents of rm are used directly as the second operand. a logical shift right (lsr) is similar, but the contents of rm are moved to less significant positions in the result. lsr #5 has the effect shown in figure 3-7 .
S3F441FX risc microcontroller arm instruction s et 3- 13 31 contents of rm value of operand 2 0 carry out 4 5 0 0 0 0 0 figure 3-7. logical shift right the form of the shift field which might be expected to correspond to lsr #0 is used to encode lsr #32, which has a zero result with bit 31 of rm as the carry output. logical shift right zero is redundant as it is the same as logical shift left zero, so the assembler will convert lsr #0 (and asr #0 and ror #0) into lsl #0, and allow lsr #32 to be specified. an arithmetic shift right (asr) is similar to logical shift right, except that the high bits are filled with bit 31 of rm instead of zeros. this preserves the sign in 2's complement notation. for example, asr #5 is shown in figure 3-8. 31 contents of rm value of operand 2 0 carry out 4 5 30 figure 3-8. arithmetic shift right the form of the shift field which might be expected to give asr #0 is used to encode asr #32. bit 31 of rm is again used as the carry output, and each bit of operand 2 is also equal to bit 31 of rm. the result is therefore all ones or all zeros, according to the value of bit 31 of rm.
arm instruction set S3F441FX risc microcontroller 3- 14 rotate right (ror) operations reuse the bits which "overshoot" in a logical shift right operation by reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right operations. for example, ror #5 is shown in figure 3-9. 31 contents of rm value of operand 2 0 carry out 4 5 figure 3-9. rotate right the form of the shift field which might be expected to give ror #0 is used to encode a special function of the barrel shifter, rotate right extended ( rrx). this is a rotate right by one bit position of the 33 bit quantity formed by appending the cpsr c flag to the most significant end of the contents of rm as shown in figure 3-10. 31 contents of rm value of operand 2 0 1 carry out c in figure 3-10. rotate right extended
S3F441FX risc microcontroller arm instruction s et 3- 15 register specified shift amount only the least significant byte of the contents of rs is used to determine the shift amount. rs can be any general register other than r15. if this byte is zero, the unchanged contents of rm will be used as the second operand, and the old value of the cpsr c flag will be passed on as the shifter carry output. if the byte has a value between 1 and 31, the shifted result will exactly match that of an instruction specified shift with the same value and shift operation. if the value in the byte is 32 or more, the result will be a logical extension of the shift described above: 1. lsl by 32 has result zero, carry out equal to bit 0 of rm. 2. lsl by more than 32 has result zero, carry out zero. 3. lsr by 32 has result zero, carry out equal to bit 31 of rm. 4. lsr by more than 32 has result zero, carry out zero. 5. asr by 32 or more has result filled with the value of bit 31 of rm, carry out equal to bit 31 of rm. 6. ror by 32 has result equal to rm, carry out equal to bit 31 of rm. 7. r or by n where n is greater than 32 will give the same result and carry out as ror by n-32; therefore repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above. note the zero in bit 7 of an instruction with a register controlled shift is compulsory; a one in this bit will cause the instruction to be a multiply or undefined instruction.
arm instruction set S3F441FX risc microcontroller 3- 16 immediate operand rotates the immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value. this value is zero extended to 32 bits, and then subject to a rotate right by twice the value in the rotate field. this enables many common constants to be generated, for example all powers of 2. writing to r15 when rd is a register other than r15, the condition code flags in the cpsr may be updated from the alu flags as described above. when rd is r15 and the s flag in the instruction is not set the result of the operation is placed in r15 and the cpsr is unaffected. when rd is r15 and the s flag is set the result of the operation is placed in r15 and the spsr corresponding to the current mode is moved to the cpsr. this allows state changes which automatically restore both pc and cpsr. this form of instruction should not be used in user mode. using r15 as an operand if r15 (the pc) is used as an operand in a data processing instruction the register is used directly. the pc value will be the address of the instruction, plus 8 or 12 bytes due to instruction pre-fetching. if the shift amount is specified in the instruction, the pc will be 8 bytes ahead. if a register is used to specify the shift amount the pc will be 12 bytes ahead. teq, tst, cmp and cmn opcodes note teq, tst, cmp and cmn do not write the result of their operation but do set flags in the cpsr. an assembler should always set the s flag for these instructions even if this is not specified in the mnemonic. the teqp form of the teq instruction used in earlier arm processors must not be used: the psr transfer operations should be used instead. the action of teqp in the arm7tdmi is to move spsr_ to the cpsr if the processor is in a privileged mode and to do nothing if in user mode. instruction cycle times data processing instructions vary in the number of incremental cycles taken as follows: table 3-4. incremental cycle times processing type cycles normal data processing 1s data processing with register specified shift 1s + 1i data processing with pc written 2s + 1n data processing with register specified shift and pc written 2s + 1n +1i note: s, n and i are as defined sequential (s-cycle), non-sequential (n-cycle), and internal (i-cycle) respectively.
S3F441FX risc microcontroller arm instruction s et 3- 17 assembler syntax mov,mvn (single operand instructions). < opcode>{ cond}{s} rd, cmp,cmn,teq,tst (instructions which do not produce a result). < opcode>{ cond} rn, and,eor,sub,rsb,add,adc,sbc,rsc,orr,bic < opcode>{ cond}{s} rd,rn, where: rm{,} or,<#expression> { cond} a two-character condition mnemonic. see table 3-2. { s} set condition codes if s present (implied for cmp, cmn, teq, tst). rd, rn and rm expressions evaluating to a register number. <#expression> if this is used, the assembler will attempt to generate a shifted immediate 8-bit field to match the expression. if this is impossible, it will give an error. < shiftname> or < shiftname> #expression, or rrx (rotate right one bit with exten d). < shiftname>s asl, lsl, lsr, asr, ror. (asl is a synonym for lsl, they assemble to the same code.) examples addeq r2,r4,r5 ; if the z flag is set make r2:=r4+r5 teqs r4,#3 ; test r4 for equality with 3. ; (the s is in fact redundant as the ; assembler inserts it automatically.) sub r4,r5,r7,lsr r2 ; logical right shift r7 by the number in ; the bottom byte of r2, subtract result ; from r5, and put the answer into r4. mov pc,r14 ; return from subroutine. movs pc,r14 ; return f rom exception and restore cpsr ; from spsr_mode.
arm instruction set S3F441FX risc microcontroller 3- 18 psr transfer (mrs, msr) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the mrs and msr instructions are formed from a subset of the data processing operations and are implemented using the teq, tst, cmn and cmp instructions without the s flag set. the encoding is shown in figure 3-11. these instructions allow access to the cpsr and spsr registers. the mrs instruction allows the contents of the cpsr or spsr_ to be moved to a general register. the msr instruction allows the contents of a general register to be moved to the cpsr or spsr_ register. the msr instruction also allows an immediate value or register contents to be transferred to the condition code flags (n,z,c and v) of cpsr or spsr_ without affecting the control bits. in this case, the top four bits of the specified register contents or 32 bit immediate value are written to the top four bits of the relevant psr. operand restrictions in user mode, the control bits of the cpsr are protected from change, so only the condition code flags of the cpsr can be changed. in other (privileged) modes the entire cpsr can be changed. note that the software must never change the state of the t bit in the cpsr. if this happens, the processor will enter an unpredictable state. the spsr register which is accessed depends on the mode at the time of execution. for example, only spsr_fiq is accessible when the processor is in fiq mode. you must not specify r15 as the source or destination register. also, do not attempt to access an spsr in user mode, since no such register exists.
S3F441FX risc microcontroller arm instruction s et 3- 19 msr (transfer register contents or immediate value to psr flag bits only) cond source operand pd 101001111 31 22 27 28 11 12 21 23 i 10 00 26 25 24 0 cond 00000000 00010 pd 101001111 31 22 27 28 11 12 21 23 rm msr (transfer register contents to psr) 4 3 0 cond 000000000000 00010 rd ps 001111 31 22 27 15 28 16 11 12 21 23 mrs (transfer psr contents to a register) 0 [3:0] source register [22] destination psr 0 = cpsr 1 = spsr_ [31:28] condition field [15:12] destination register [22] source psr 0 = cpsr 1 = spsr_ [31:28] condition field [3:0] source register [11:4] source operand is an immediate value [7:0] unsigned 8 bit immediate value [11:8] rotate applied to imm [22] destination psr 0 = cpsr 1 = spsr_ [25] immediate operand 0 = source operand is a register 1 = source operand is a immediate value [11:0] source operand [31:28] condition field 00000000 rm 11 4 3 0 rotate imm 11 0 8 7 figure 3-11. psr transfer
arm instruction set S3F441FX risc microcontroller 3- 20 reserved bits only twelve bits of the psr are defined in arm7tdmi (n,z,c,v,i,f, t & m[4:0]); the remaining bits are reserved for use in future versions of the processor. refer to figure 2-6 for a full description of the psr bits. to ensure the maximum compatibility between arm7tdmi programs and future processors, the following rules should be observed: the reserved bits should be preserved when changing the value in a psr. programs should not rely on specific values from the reserved bits when checking the psr status, since they may read as one or zero in future processors. a read-modify-write strategy should therefore be used when altering the control bits of any psr register; this involves transferring the appropriate psr register to a general register using the mrs instruction, changing only the relevant bits and then transferring the modified value back to the psr register using the msr instruction. examples the following sequence performs a mode change: mrs r0,cpsr ; take a copy of the cpsr. bic r0,r0,#0x1f ; clear the mode bits. orr r0,r0,#new_mode ; select new mode msr cpsr,r0 ; write back the modified cpsr. when the aim is simply to change the condition code flags in a psr, a value can be written directly to the flag bits without disturbing the control bits. the following instruction sets the n,z,c and v flags: msr cpsr_flg,#0xf0000000 ; set all the flags regardless of their previous state ; (does not affect any control bits). no attempt should be made to write an 8 bit immediate value into the whole psr since such an operation cannot preserve the reserved bits. instruction cycle times psr transfers take 1s incremental cycles, where s is defined as sequential (s-cycle).
S3F441FX risc microcontroller arm instruction s et 3- 21 assembly syntax mrs - transfer psr contents to a register mrs{ cond} rd, msr - transfer register contents to psr msr{ cond} < psr>, rm msr - transfer register contents to psr flag bits only msr{ cond} < psrf>, rm the most significant four bits of the register contents are written to the n,z,c & v flags respectively. msr - transfer immediate value to psr flag bits only msr{ cond} < psrf>,<#expression> the expression should symbolise a 32 bit value of which the most significant four bits are written to the n,z,c and v flags respectively. key: { cond} two-character condition mnemonic. see table 3-2.. rd and rm expressions evaluating to a register number other than r15 < psr> cpsr, cpsr_all, spsr or spsr_all. (cpsr and cpsr_all are synonyms as are spsr and spsr_all) < psrf> cpsr_flg or spsr_flg <#expression> where this is used, the assembler will attempt to generate a shifted immediate 8-bit field to match the expression. if this is impossible, it will give an error. examples in user mode the instructions behave as follows: msr cpsr_all,rm ; cpsr[31:28] ? rm[31:28] msr cpsr_flg,rm ; cpsr[31:28] ? rm[31:28] msr cpsr_flg,#0xa0000000 ; cpsr[31:28] ? 0xa (set n,c; clear z,v) mrs rd,cpsr ; rd[31:0] ? cpsr[31:0] in privileged modes the instructions behave as follows: msr cpsr_all,rm ; cpsr[31:0] ? rm[31:0] msr cpsr_flg,rm ; cpsr[31:28] ? rm[31:28] msr cpsr_flg,#0x50000000 ; cpsr[31:28] ? 0x5 (set z,v; clear n,c) msr spsr_all,rm ; spsr_[31:0] ? rm[31:0] msr spsr_flg,rm ; spsr_[31:28] ? rm[31:28] msr spsr_flg,#0xc0000000 ; spsr_[31:28] ? 0xc (set n,z; clear c,v) mrs rd,spsr ; rd[31:0] ? spsr_[31:0]
arm instruction set S3F441FX risc microcontroller 3- 22 multiply and multiply-accumulate (mul, mla) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-12. the multiply and multiply-accumulate instructions use an 8 bit booth's algorithm to perform integer multiplication. 31 27 19 15 cond 28 16 11 12 21 20 s rd rn [15:12][11:8][3:0] operand registers [19:16] destination register [20] set condition code 0 = do not alter condition codes 1 = set condition codes [21] accumulate 0 = multiply only 1 = multiply and accumulate [31:28] condition field 22 1 0 0 1 rs rm a 0 0 0 0 0 0 8 7 4 3 0 figure 3-12. multiply instructions the multiply form of the instruction gives rd=rm rs. rn is ignored, and should be set to zero for compatibility with possible future upgrades to the instruction set. the multiply-accumulate form gives rd=rm rs+rn, which can save an explicit add instruction in some circumstances. both forms of the instruction work on operands which may be considered as signed (2's complement) or unsigned integers. the results of a signed multiply and of an unsigned multiply of 32 bit operands differ only in the upper 32 bits - the low 32 bits of the signed and unsigned results are identical. as these instructions only produce the low 32 bits of a multiply, they can be used for both signed and unsigned multiplies. for example consider the multiplication of the operands: operand a operand b result 0xfffffff6 0x0000001 0xffffff38
S3F441FX risc microcontroller arm instruction s et 3- 23 if the operands are interpreted as signed operand a has the value -10, operand b has the value 20, and the result is -200 which is correctly represented as 0xffffff38. if the operands are interpreted as unsigned operand a has the value 4294967286, operand b has the value 20 and the result is 85899345720, which is represented as 0x13ffffff38, so the least significant 32 bits are 0xffffff38. operand restrictions the destination register rd must not be the same as the operand register rm. r15 must not be used as an operand or as the destination register. all other register combinations will give correct results, and rd, rn and rs may use the same register when required.
arm instruction set S3F441FX risc microcontroller 3- 24 cpsr flags setting the cpsr flags is optional, and is controlled by the s bit in the instruction. the n (negative) and z (zero) flags are set correctly on the result (n is made equal to bit 31 of the result, and z is set if and only if the result is zero). the c (carry) flag is set to a meaningless value and the v ( overflow) flag is unaffected. instruction cycle times mul takes 1s + mi and mla 1s + (m+1)i cycles to execute, where s and i are defined as sequential (s-cycle) and internal (i-cycle), respectively. m the number of 8 bit multiplier array cycles is required to complete the multiply, which is controlled by th e value of the multiplier operand specified by rs. its possible values are as follows 1 if bits [32:8] of the multiplier operand are all zero or all one. 2 if bits [32:16] of the multiplier operand are all zero or all one. 3 if bits [32:24] of the multiplier operand are all zero or all one. 4 in all other cases. assembler syntax mul{ cond}{s} rd,rm,rs mla{ cond}{s} rd,rm,rs,rn { cond} two-character condition mnemonic. see table 3-2.. { s} set condition codes if s present rd, rm, rs and rn expressions evaluating to a register number other than r15. examples mul r1,r2,r3 ; r1:=r2*r3 mlaeqs r1,r2,r3,r4 ; conditionally r1:=r2*r3+r4, setting condition codes.
S3F441FX risc microcontroller arm instruction s et 3- 25 multiply long and multiply-accumulate long (mull, mlal) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-13. the multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results. signed and unsigned multiplication each with optional accumulate give rise to four variations. 31 27 19 15 cond 28 16 11 12 21 23 u 20 s rdhi rdlo [11:8][3:0] operand registers [19:16][15:12] source destination registers [20] set condition code 0 = do not alter condition codes 1 = set condition codes [21] accumulate 0 = multiply only 1 = multiply and accumulate [22] unsigned 0 = unsigned 1 = signed [31:28] condition field 22 0 0 0 0 1 1 0 0 1 rs rm a 8 7 4 3 0 figure 3-13. multiply long instructions the multiply forms (umull and smull) take two 32 bit numbers and multiply them to produce a 64 bit result of the form rdhi,rdlo := rm * rs. the lower 32 bits of the 64 bit result are written to rdlo, the upper 32 bits of the result are written to rdhi. the multiply-accumulate forms (umlal and smlal) take two 32 bit numbers, multiply them and add a 64 bit number to produce a 64 bit result of the form rdhi,rdlo := rm * rs + rdhi,rdlo. the lower 32 bits of the 64 bit number to add is read from rdlo. the upper 32 bits of the 64 bit number to add is read from rdhi. the lower 32 bits of the 64 bit result are written to rdlo. the upper 32 bits of the 64 bit result are written to rdhi. the umull and umlal instructions treat all of their operands as unsigned binary numbers and write an unsigned 64 bit result. the smull and smlal instructions treat all of their operands as two's-complement signed numbers and write a two's-complement signed 64 bit result.
arm instruction set S3F441FX risc microcontroller 3- 26 operand restrictions r15 must not be used as an operand or as a destination register. rdhi, rdlo, and rm must all specify different registers. cpsr flags setting the cpsr flags is optional, and is controlled by the s bit in the instruction. the n and z flags are set correctly on the result (n is equal to bit 63 of the result, z is set if and only if all 64 bits of the result are zero). both the c and v flags are set to meaningless values. instruction cycle times mull takes 1s + (m+1)i and mlal 1s + (m+2)i cycles to execute, where m is the number of 8 bit multiplier array cycles required to complete the multiply, which is controlled by the value of the multiplier operand specified by rs. its possible values are as follows: for signed instructions smull, smlal: if bits [31:8] of the multiplier operand are all zero or all one. if bits [31:16] of the multiplier operand are all zero or all one. if bits [31:24] of the multiplier operand are all zero or all one. in all other cases. for unsigned instructions umull, umlal: if bits [31:8] of the multiplier operand are all zero. if bits [31:16] of the multiplier operand are all zero. if bits [31:24] of the multiplier operand are all zero. in all other cases. s and i are defined as sequential (s-cycle) and internal (i-cycle), respectively.
S3F441FX risc microcontroller arm instruction s et 3- 27 assembler syntax table 3-5. assembler syntax descriptions mnemonic description purpose umull{ cond}{s} rdlo,rdhi,rm,rs unsigned multiply long 32 x 32 = 64 umlal{ cond}{s} rdlo,rdhi,rm,rs unsigned multiply & accumulate long 32 x 32 + 64 = 64 smull{ cond}{s} rdlo,rdhi,rm,rs signed multiply long 32 x 32 = 64 smlal{ cond}{s} rdlo,rdhi,rm,rs signed multiply & accumulate long 32 x 32 + 64 = 64 where: { cond} two-character condition mnemonic. see table 3-2. {s} set condition codes if s present rdlo, rdhi, rm, rs expressions evaluating to a register number other than r15. examples umull r1,r4,r2,r3 ; r4,r1:=r2*r3 umlals r1,r5,r2, r3 ; r5,r1:=r2*r3+r5,r1 also setting condition codes
arm instruction set S3F441FX risc microcontroller 3- 28 single data transfer (ldr, str) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-14. the single data transfer instructions are used to load or store single bytes or words of data. the memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register. the result of this calculation may be written back into the base register if auto-indexing is required. 31 27 19 15 0 cond 28 16 11 12 21 23 b 20 l rn rd 22 01 i p u offset w 26 24 25 [15:12] source/destination registers [19:16] base register [20] load/store bit 0 = store to memory 1 = load from memory [21] write-back bit 0 = no write-back 1 = write address into base [22] byte/word bit 0 = transfer word quantity 1 = transfer byte quantity [23] up/down bit 0 = down: subtract offset from base 1 = up: add offset to base [24] pre/post indexing bit 0 = post: add offset after transfer 1 = pre: add offset before transfer [25] immediate offset 0 = offset is an immediate value 1 = offset is an register value [11:0] offset shift immediate [11:0] unsigned 12-bit immediate offset 11 11 rm [3:0] offset register [11:4] shift applied to rm [31:28] condition field 0 4 3 0 figure 3-14. single data transfer instructions
S3F441FX risc microcontroller arm instruction s et 3- 29 offsets and auto-indexing the offset from the base may be either a 12 bit unsigned binary immediate value in the instruction, or a second register (possibly shifted in some way). the offset may be added to (u=1) or subtracted from (u=0) the base register rn. the offset modification may be performed either before (pre-indexed, p=1) or after (post-indexed, p=0) the base is used as the transfer address. the w bit gives optional auto increment and decrement addressing modes. the modified base value may be written back into the base (w=1), or the old base value may be kept (w=0). in the case of post-indexed addressing, the write back bit is redundant and is always set to zero, since the old base value can be retained by setting the offset to zero. therefore post-indexed data transfers always write back the modified base. the only use of the w bit in a post-indexed data transfer is in privileged mode code, where setting the w bit forces non- privileged mode for the transfer, allowing the operating system to generate a user address in a system where the memory management hardware makes suitable use of this hardware. shifted register offset the 8 shift control bits are described in the data processing instructions section. however, the register specified shift amounts are not available in this instruction class. see figure 3-5. bytes and words this instruction class may be used to transfer a byte (b=1) or a word (b=0) between an arm7tdmi register and memory. the action of ldr(b) and str(b) instructions is influenced by the bigend control signal of arm7tdmi core. the two possible configurations are described below. little- endian configuration a byte load (ldrb) expects the data on data bus inputs 7 through 0 if the supplied address is on a word boundary, on data bus inputs 15 through 8 if it is a word address plus one byte, and so on. the selected byte is placed in the least significant 8 bits of the destination register, and the remaining bits of the register are filled with zeros. please see figure 2-2. a byte store (strb) repeats the least significant 8 bits of the source register four times across data bus outputs 31 through 0. the external memory system should activate the appropriate byte subsystem to store the data. a word load (ldr) will normally use a word aligned address. however, an address offset from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 0 to 7. this means that half-words accessed at offsets 0 and 2 from the word boundary will be correctly loaded into bits 0 through 15 of the register. two shift operations are then required to clear or to sign extend the upper 16 bits. a word store (str) should generate a word aligned address. the word presented to the data bus is not affected if the address is not word aligned. that is, bit 31 of the register being stored always appears on data bus output 31.
arm instruction set S3F441FX risc microcontroller 3- 30 ldr from word aligned address a+3 a a+2 a+1 memory 24 16 8 0 a b c d register 24 16 8 0 a b c d ldr from address offset by 2 a+3 a a+2 a+1 memory 24 16 8 0 a b c d register 24 16 8 0 a b c d figure 3-15. little- endian offset addressing big- endian configuration a byte load (ldrb) expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary, on data bus inputs 23 through 16 if it is a word address plus one byte, and so on. the selected byte is placed in the least significant 8 bits of the destination register and the remaining bits of the register are filled with zeros. please see figure 2-1. a byte store (strb) repeats the least significant 8 bits of the source register four times across data bus outputs 31 through 0. the external memory system should activate the appropriate byte subsystem to store the data. a word load (ldr) should generate a word aligned address. an address offset of 0 or 2 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24. this means that half-words accessed at these offsets will be correctly loaded into bits 16 through 31 of the register. a shift operation is then required to move (and optionally sign extend) the data into the bottom 16 bits. an address offset of 1 or 3 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 15 through 8. a word store (str) should generate a word aligned address. the word presented to the data bus is not affected if the address is not word aligned. that is, bit 31 of the register being stored always appears on data bus output 31.
S3F441FX risc microcontroller arm instruction s et 3- 31 use of r15 write-back must not be specified if r15 is specified as the base register ( rn). when using r15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction. r15 must not be specified as the register offset ( rm). when r15 is the source register (rd) of a register store (str) instruction, the stored value will be address of the instruction plus 12. restriction on the use of base register when configured for late aborts, the following example code is difficult to unwind as the base register, rn, gets updated before the abort handler starts. sometimes it may be impossible to calculate the initial value. after an abort, the following example code is difficult to unwind as the base register, rn, gets updated before the abort handler starts. sometimes it may be impossible to calculate the initial value. example: ldr r0,[r1],r1 therefore a post-indexed ldr or str where rm is the same register as rn should not be used. data aborts a transfer to or from a legal address may cause problems for a memory management system. for instance, in a system which uses virtual memory the required data may be absent from main memory. the memory manager can signal a problem by taking the processor abort input high whereupon the data abort trap will be taken. it is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued. instruction cycle times normal ldr instructions take 1s + 1n + 1i and ldr pc take 2s + 2n +1i incremental cycles, where s,n and i are defined as squential (s-cycle), non-sequential (n-cycle), and internal (i-cycle), respectively. str instructions take 2n incremental cycles to execute.
arm instruction set S3F441FX risc microcontroller 3- 32 assembler syntax { cond}{b}{t} rd,

where: ldr load from memory into a re gister str store from a register into memory { cond} two-character condition mnemonic. see table 3-2. { b} if b is present then byte transfer, otherwise word transfer { t} if t is present the w bit will be set in a post-indexed instruction, forcing non-privileged mode for the transfer cycle. t is not allowed when a pre-indexed addressing mode is specified or implied. rd an expression evaluating to a valid register number. rn and rm expressions evaluating to a register number. if rn is r15 then the assembler will subtract 8 from the offset value to allow for arm7tdmi pipelining. in this case base write-back should not be specified.

ldr load from memory into a register str store from a register into memory { cond} two-character condition mnemonic. see table 3-2.. h transfer half-word quantity sb load sign extended byte (only valid for ldr) sh load sign extended half-word (only valid for ldr) rd an expression evaluating to a valid register number.

ldc load from memory to coprocessor stc store from coprocessor to memory { l} when present perform long transfer (n=1), otherwise perform short transfer (n=0) { cond} two character condition mnemonic. see table 3-2.. p# the unique number of the required coprocessor cd an expression evaluating to a valid coprocessor register number that is placed in the crd field

can be: 1 an expression which generates an addr ess: the assembler will attempt to generate an instruction using the pc as a base and a corrected immediate offset to address the location given by evaluating the expression. this will be a pc relative, pre-indexed address. if the address is out of range, an error will be generated 2 a pre-indexed addressing specification: [ rn] offset of zero [ rn,<#expression>]{!} offset of bytes 3 a post-indexed addressing specification: [ rn],<#expression offset of bytes {!} write back the base register (set the w bit) if! is present rn is an expression evaluating to a valid arm7tdmi register number. note if rn is r15, the assembler will subtract 8 from the offset value to allow for arm7tdmi pipelining. examples ldc p1,c2,table ; load c2 of coprocessor 1 from address ; table, using a pc relative address. stceql p2,c3,[r5,#24]! ; conditionally store c3 of coprocessor 2 ; into an address 24 bytes up from r5, ; write this address ba ck to r5, and use ; long transfer option (probably to store multiple words). note although the address offset is expressed in bytes, the instruction offset field is in words. the assembler will adjust the offset appropriately.
arm instruction set S3F441FX risc microcontroller 3- 56 coprocessor register transfers (mrc, mcr) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-27. this class of instruction is used to communicate information directly between arm7tdmi and a coprocessor. an example of a coprocessor to arm7tdmi register transfer (mrc) instruction would be a fix of a floating point value held in a coprocessor, where the floating point number is converted into a 32 bit integer within the coprocessor, and the result is then transferred to arm7tdmi register. a float of a 32 bit value in arm7tdmi register into a floating point value within the coprocessor illustrates the use of arm7tdmi register to coprocessor transfer (mcr). an important use of this instruction is to communicate control information directly from the coprocessor into the arm7tdmi cpsr flags. as an example, the result of a comparison of two floating point values within a coprocessor can be moved to the cpsr to control the subsequent flow of execution. 31 27 19 15 cond 28 16 11 12 21 23 20 l crn rd [3:0] coprocessor operand register [7:5] coprocessor information [11:8] coprocessor number [15:12] arm source/destination register [19:16] coprocessor source/destination register [20] load/store bit 0 = store to coprocessor 1 = load from coprocessor [21] coprocessor operation mode [31:28] condition field 1110 cp opc cp# 24 crm 1 cp 8 7 5 4 3 0 figure 3-27. coprocessor register transfer instructions the coprocessor fields the cp# field is used, as for all coprocessor instructions, to specify which coprocessor is being called upon. the cp opc, crn, cp and crm fields are used only by the coprocessor, and the interpretation presented here is derived from convention only. other interpretations are allowed where the coprocessor functionality is incompatible with this one. the conventional interpretation is that the cp opc and cp fields specify the operation the coprocessor is required to perform, crn is the coprocessor register which is the source or destination of the transferred information, and crm is a second coprocessor register which may be involved in some way which depends on the particular operation specified.
S3F441FX risc microcontroller arm instruction s et 3- 57 transfers to r15 when a coprocessor register transfer to arm7tdmi has r15 as the destination, bits 31, 30, 29 and 28 of the transferred word are copied into the n, z, c and v flags respectively. the other bits of the transferred word are ignored, and the pc and other cpsr bits are unaffected by the transfer. transfers from r15 a coprocessor register transfer from arm7tdmi with r15 as the source register will store the pc+12. instruction cycle times mrc instructions take 1s + (b+1)i +1c incremental cycles to execute, where s, i and c are defined as sequential (s-cycle), internal (i-cycle), and coprocessor register transfer (c-cycle), respectively. mcr instructions take 1s + bi +1c incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop. assembler syntax { cond} p#,,rd,cn,cm{,} mrc move from coprocessor to arm7tdmi register (l=1) mcr move from arm7tdmi register to cop rocessor (l=0) { cond} two character condition mnemonic. see table 3-2 p# the unique number of the required coprocessor evaluated to a constant and placed in the cp opc field rd an expression evaluating to a valid arm7tdmi register number cn and cm expressions evaluating to the valid coprocessor register numbers crn and crm respectively where present is evaluated to a constant and placed in the cp field examples mrc p2,5,r3,c5,c6 ; request coprocessor 2 to per form operation 5 ; on c5 and c6, and transfer the (single ; 32-bit word) result back to r3. mcr p6,0,r4,c5,c6 ; request coprocessor 6 to perform operation 0 ; on r4 and place the result in c6. mrceq p3,9,r3,c5,c6,2 ; conditionally request coprocessor 3 to ; perform operation 9 (type 2) on c5 and ; c6, and transfer the result back to r3.
arm instruction set S3F441FX risc microcontroller 3- 58 undefined instruction the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction format is shown in figure 3-28. 31 27 cond 28 25 24 011 xxxxxxxxxxxxxxxxxxxx 1 xxxx 5 4 3 0 figure 3-28. undefined instruction if the condition is true, the undefined instruction trap will be taken. note that the undefined instruction mechanism involves offering this instruction to any coprocessors which may be present, and all coprocessors must refuse to accept it by driving cpa and cpb high. instruction cycle times this instruction takes 2s + 1i + 1n cycles, where s, n and i are defined as squential (s-cycle), non-sequential (n-cycle), and internal (i-cycle). assembler syntax the assembler has no mnemonics for generating this instruction. if it is adopted in the future for some specified use, suitable mnemonics will be added to the assembler. until such time, this instruction must not be used.
S3F441FX risc microcontroller arm instruction s et 3- 59 instruction set examples the following examples show ways in which the basic arm7tdmi instructions can combine to give efficient code. none of these methods saves a great deal of execution time (although they may save some), mostly they just save code. using the conditional instructions using conditionals for logical or cmp rn,#p ; if rn=p or rm=q then goto label. beq label cmp rm,#q beq label this can be replaced by cmp rn,#p cmpne rm,#q ; if condition not satisfied try other test. beq label absolute value teq rn,#0 ; test sign rsbmi rn,rn,#0 ; and 2's complement if necessary. multiplication by 4, 5 or 6 (run time) mov rc,ra,lsl#2 ; multiply by 4, cmp rb,#5 ; test value, addcs rc,rc,ra ; complete multiply by 5, addhi rc,rc,ra ; complete m ultiply by 6. combining discrete and range tests teq rc,#127 ; discrete test, cmpne rc,# " "-1 ; range test movls rc,# "" ; if rc<= "" or rc=ascii(127) ; then rc:= "."
arm instruction set S3F441FX risc microcontroller 3- 60 division and remainder a number of divide routines for specific applications are provided in source form as part of the ansi c library provided with the arm cross development toolkit, available from your supplier. a short general purpose divide routine follows. ; enter with numbers in ra and rb. mov rcnt,#1 ; bit to control the d ivision. div1 cmp rb,#0x80000000 ; move rb until greater than ra. cmpcc rb,ra movcc rb,rb,asl#1 movcc rcnt,rcnt,asl#1 bcc div1 mov rc,#0 div2 cmp ra,rb ; test for possible subtraction. subcs ra,ra,rb ; subtract if ok, addcs rc,rc,rcnt ; put relevant bit into result movs rcnt,rcnt,lsr#1 ; shift control bit movne rb,rb,lsr#1 ; halve unless finished. bne div2 ; divide result in rc, remainder in ra. overflow eetection in the arm7tdmi 1. overflow in unsigned multiply with a 32-bit result umull rd,rt,rm,rn ; 3 to 6 cycles teq rt,#0 ; +1 cycle and a register bne overflow 2. overflow in signed multiply with a 32-bit result smull rd,rt,rm,rn ; 3 to 6 cycles teq rt,rd asr#31 ; +1 cycle and a register bne overflow 3. overflow in unsigned multiply accumulate with a 32 bit result umlal rd,rt,rm,rn ; 4 to 7 cycles teq rt,#0 ; +1 cycle and a register bne overflow 4. overflow in signed multiply accumulate with a 32 bit result smlal rd,rt,rm,rn ; 4 to 7 cycles teq rt,rd, asr#31 ; +1 cycle and a register bne overflow
S3F441FX risc microcontroller arm instruction s et 3- 61 5. overflow in unsigned multiply accumulate with a 64 bit result umull rl,rh,rm,rn ; 3 to 6 cycles adds rl,rl,ra1 ; lower accumulate adc rh,rh,ra2 ; upper accumulate bcs overflow ; 1 cycle and 2 registers 6. overflow in signed multiply accumulate with a 64 bit result smull rl,rh,rm,rn ; 3 to 6 cycles adds rl,rl,ra1 ; lower accumulate adc rh,rh,ra2 ; upper accumulate bvs overflow ; 1 cycle and 2 registers note overflow checking is not applicable to unsigned and signed multiplies with a 64-bit result, since overflow does not occur in such calculations. pseudo-random binary sequence generator it is often necessary to generate (pseudo-) random numbers and the most efficient algorithms are based on shift generators with exclusive-or feedback rather like a cyclic redundancy check generator. unfortunately the sequence of a 32 bit generator needs more than one feedback tap to be maximal length (i.e. 2^32-1 cycles before repetition), so this example uses a 33 bit register with taps at bits 33 and 20. the basic algorithm is newbit:=bit 33 eor bit 20, shift left the 33 bit number and put in newbit at the bottom; this operation is performed for all the newbits needed (i.e. 32 bits). the entire operation can be done in 5 s cycles: ; enter with seed in ra (32 bits), ; rb (1 bit in rb lsb), uses rc. tst rb,rb,lsr#1 ; top bit into carry movs rc,ra,rrx ; 33 bit rotate right adc rb,rb,rb ; carry into lsb of rb eor rc,rc,ra,lsl#12 ; (involved!) eor ra,rc,rc,lsr#20 ; (similarly involved!) new seed in ra, rb as before multiplication by constant using the barrel shifter multiplication by 2^n (1,2,4,8,16,32..) mov ra, rb, lsl #n multiplication by 2^n+1 (3,5,9,17..) add ra,ra,ra,lsl #n multiplication by 2^n-1 (3,7,15..) rsb ra,ra,ra,lsl #n
arm instruction set S3F441FX risc microcontroller 3- 62 multiplication by 6 add ra,ra,ra,lsl #1 ; multiply by 3 mov ra,ra,lsl#1 ; and then by 2 multiply by 10 and add in extra number add ra,ra,ra,lsl#2 ; multiply by 5 add ra,rc,ra,lsl#1 ; multiply by 2 and add in next digit general recursive method for rb := ra*c, c a constant: 1. if c even, say c = 2^n*d, d odd: d=1: mov rb,ra,lsl #n d<>1: { rb := ra*d} mov rb,rb,lsl #n 2. if c mod 4 = 1, say c = 2^n*d+1, d odd, n>1: d=1: add rb,ra,ra,lsl #n d<>1: { rb := ra*d} add rb,ra,rb,lsl #n 3. if c mod 4 = 3, say c = 2^n*d-1, d odd, n>1: d=1: rsb rb,ra,ra,lsl #n d<>1: { rb := ra*d} rsb rb,ra,rb,lsl #n this is not quite optimal, but close. an example of its non-optimality is multiply by 45 which is done by: rsb rb,ra,ra,lsl#2 ; multiply by 3 rsb r b,ra,rb,lsl#2 ; multiply by 4*3-1 = 11 add rb,ra,rb,lsl# 2 ; multiply by 4*11+1 = 45 rather than by: add rb,ra,ra,lsl#3 ; multiply by 9 add rb,rb,rb,lsl#2 ; multiply by 5*9 = 45
S3F441FX risc microcontroller arm instruction s et 3- 63 loading a word from an unknown alignment ; enter with address in ra (32 bits) uses ; rb, rc result in rd. note d must be less than c e.g. 0,1 bic rb,ra,#3 ; get word aligned address ldmia rb,{ rd,rc} ; get 64 bits containing answer and rb,ra,#3 ; correction factor in bytes movs rb,rb,lsl#3 ; ...now in bits and t est if aligned movne rd,rd,lsr rb ; produce bottom of result word (if not aligned) rsbne rb,rb,#32 ; get other shift amount orrne rd,rd,rc,lsl rb ; combine two halves to get result
arm instruction set S3F441FX risc microcontroller 3- 64 notes
S3F441FX risc microcontroller arm instruction s et 3- 65 thumb instruction set format the thumb instruction sets are 16-bit versions of arm instruction sets (32-bit format). the arm instructions are reduced to 16-bit versions, thumb instructions, at the cost of versatile functions of the arm instruction sets. the thumb instructions are decompressed to the arm instructions by the thumb decompressor inside the arm7tdmi core. as the thumb instructions are compressed arm instructions, the thumb instructions have the 16-bit format instructions and have some restrictions. the restrictions by 16-bit format is fully notified for using the thumb instructions. format summary the thumb instruction set formats are shown in the following figure. move shifted register 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 l 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 l 1 0 r 1 1 0 1 0 sp 1 l l s h 0 0 1 b l 0 1 h 0 1 b 0 0 1 1 1 i op op op op op l 0 s 1 offset5 rs rd rn/offset3 rd rs rd offset8 rs rd/hd rd h1 h2 rs/hs rd word8 rd rb ro ro rb rd offset5 rb rd rb rd offset5 rd rd word8 word8 sword7 rb cond rlist rlist softset8 value8 offset11 offset add/subtract move/compare/add/ subtract immediate alu operations hi register operations /branch exchange pc-relative load load/store with register offset load/store with immediate offset load/store sign-extended byte/halfword load/store halfword sp-relative load/store load address add offset to stack pointer push/pop register multiple load/store conditional branch software interrupt unconditional branch long branch with link 15 14 13 12 11 10 9 8 7 6 5 4 2 3 1 0 15 14 13 12 11 10 9 8 7 6 5 4 2 3 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 figure 3-29. thumb instruction set formats
arm instruction set S3F441FX risc microcontroller 3- 66 opcode summary the following table summarizes the thumb instruction set. for further information about a particular instruction please refer to the sections listed in the right-most column. table 3-7. thumb instruction set opcodes mnemonic instruction lo-register operand hi-register operand condition codes set adc add with carry y ? y add add y ? y (1) and and y ? y asr arithmetic shift right y ? y b unconditional branch y ? ? bxx conditional branch y ? ? bic bit clear y ? y bl branch and link ? ? ? bx branch and exchange y y ? cmn compare negative y ? y cmp compare y y y eor eor y ? y ldmia load multiple y ? ? ldr load word y ? ? ldrb load byte y ? ? ldrh load half-word y ? ? lsl logical shift left y ? y ldsb load sign-extended byte y ? ? ldsh load sign-extended half-word y ? ? lsr logical shift right y ? y mov move register y y y (2) mul multiply y ? y mvn move negative register y ? y
S3F441FX risc microcontroller arm instruction s et 3- 67 table 3-7. thumb instruction set opcodes (continued) mnemonic instruction lo-register operand hi-register operand condition codes set neg negate y ? y orr or y ? y pop pop register y ? ? push push register y ? ? ror rotate right y ? y sbc subtract with carry y ? y stmia store multiple y ? ? str store word y ? ? strb store byte y ? ? strh store half-word y ? ? swi software interrupt ? ? ? sub subtract y ? y tst test bits y ? y notes: 1. the condition codes are unaffected by the format 5, 12 and 13 versions of this instruction. 2. the condition codes are unaffected by the format 5 version of this instruction.
arm instruction set S3F441FX risc microcontroller 3- 68 format 1: move shifted register 15 0 0 14 10 [2:0] destination register [5:3] source register [10:6] immediate vale [12:11] opcode 0 = lsl 1 = lsr 2 = asr offset5 6 5 3 2 rd 0 0 13 12 11 op rs figure 3-30. format 1 operation these instructions move a shifted value between lo registers. the thumb assembler syntax is shown in table 3-8. note all instructions in this group set the cpsr condition codes. table 3-8. summary of format 1 instructions op thumb assembler arm equipment action 00 lsl rd, rs, #offset5 movs rd, rs, lsl #offset5 shift rs left by a 5-bit immediate value and store the result in rd. 01 lsr rd, rs, #offset5 movs rd, rs, lsr #offset5 perform logical shift right on rs by a 5-bit immediate value and store the result in rd. 10 asr rd, rs, #offset5 movs rd, rs, asr #offset5 perform arithmetic shift right on rs by a 5-bit immediate value and store the result in rd.
S3F441FX risc microcontroller arm instruction s et 3- 69 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-8. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples lsr r2, r5, #27 ; logi cal shift right the contents ; of r5 by 27 and store the result in r2. ; set condition codes on the result.
arm instruction set S3F441FX risc microcontroller 3- 70 format 2: add/subtract 15 0 14 10 [2:0] destination register [5:3] source register [8:6] register/immediate vale [9] opcode 0 = add 1 = sub [10] immediate flag 0 = register operand 1 = immediate oerand rn/offset3 rd 0 0 13 12 11 op rs 9 8 1 1 1 6 5 3 2 0 figure 3-31. format 2 operation these instructions allow the contents of a lo register or a 3-bit immediate value to be added to or subtracted from a lo register. the thumb assembler syntax is shown in table 3-9. note all instructions in this group set the cpsr condition codes. table 3-9. summary of format 2 instructions op i thumb assembler arm equipment action 0 0 add rd, rs, rn adds rd, rs, rn add contents of rn to contents of rs. place result in rd. 0 1 add rd, rs, #offset3 adds rd, rs, #offset3 add 3-bit immediate value to contents of rs. place result in rd. 1 0 sub rd, rs, rn subs rd, rs, rn subtract contents of rn from contents of rs. place result in rd. 1 1 sub rd, rs, #offset3 subs rd, rs, #offset3 subtract 3-bit immediate value from contents of rs. place result in rd.
S3F441FX risc microcontroller arm instruction s et 3- 71 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-9. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples add r0, r3, r4 ; r0 := r3 + r4 and set condition codes on the result. sub r6, r2, #6 ; r6 := r2 - 6 and set condition codes.
arm instruction set S3F441FX risc microcontroller 3- 72 format 3: move/compare/add/subtract immediate 15 0 0 14 10 [7:0] immediate vale [10:8] source/destination register [12:11] opcode 0 = mov 1 = cmp 2 = add 3 = sub offset8 rd 0 0 13 12 11 op 7 8 figure 3-32. format 3 operations the instructions in this group perform operations between a lo register and an 8-bit immediate value. the thumb assembler syntax is shown in table 3-10. note all instructions in this group set the cpsr condition codes. table 3-10. summary of format 3 instructions op thumb assembler arm equipment action 00 mov rd, #offset8 movs rd, #offset8 move 8-bit immediate value into rd. 01 cmp rd, #offset8 cmp rd, #offset8 compare contents of rd with 8-bit immediate value. 10 add rd, #offset8 adds rd, rd, #offset8 add 8-bit immediate value to contents of rd and place the result in rd. 11 sub rd, #offset8 subs rd, rd, #offset8 subtract 8-bit immediate value from contents of rd and place the result in rd.
S3F441FX risc microcontroller arm instruction s et 3- 73 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-10. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples mov r0, #128 ; r0 := 128 and set condition codes cmp r2, #62 ; set condition codes on r2 - 62 add r1, #255 ; r1 := r1 + 255 and set condition codes sub r6, #145 ; r6 := r6 - 145 and set condition codes
arm instruction set S3F441FX risc microcontroller 3- 74 format 4: alu operations 15 0 0 14 10 [2:0] source/destination register [5:3] source register 2 [9:6] opcode 5 6 3 rd 0 0 13 12 11 op rs 0 0 0 9 2 figure 3-33. format 4 operation the following instructions perform alu operations on a lo register pair. note all instructions in this group set the cpsr condition codes. table 3-11. summary of format 4 instructions op thumb assembler arm equipment action 0000 and rd, rs ands rd, rd, rs rd:= rd and rs 0001 eor rd, rs eors rd, rd, rs rd:= rd eor rs 0010 lsl rd, rs movs rd, rd, lsl rs rd := rd << rs 0011 lsr rd, rs movs rd, rd, lsr rs rd := rd >> rs 0100 asr rd, rs movs rd, rd, asr rs rd := rd asr rs 0101 adc rd, rs adcs rd, rd, rs rd := rd + rs + c-bit 0110 sbc rd, rs sbcs rd, rd, rs rd := rd - rs - not c-bit 0111 ror rd, rs movs rd, rd, ror rs rd := rd ror rs 1000 tst rd, rs tst rd, rs set condition codes on rd and rs 1001 neg rd, rs rsbs rd, rs, #0 rd = - rs 1010 cmp rd, rs cmp rd, rs set condition codes on rd - rs 1011 cmn rd, rs cmn rd, rs set condition codes on rd + rs 1100 orr rd, rs orrs rd, rd, rs rd := rd or rs 1101 mul rd, rs muls rd, rs, rd rd := rs * rd 1110 bic rd, rs bics rd, rd, rs rd := rd and not rs 1111 mvn rd, rs mvns rd, rs rd := not rs
S3F441FX risc microcontroller arm instruction s et 3- 75 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-11. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples eor r3, r4 ; r3 := r3 eor r4 and set condition codes ror r1, r0 ; rotate right r1 by the value in r0, store ; the result in r1 and set condition codes neg r5, r3 ; subtract the contents of r3 from zero, ; store the result in r5. set condition codes ie r5 = - r3 cmp r2, r6 ; set the condition codes on the result of r2 - r6 mul r0, r7 ; r0 := r7 * r0 and set conditi on codes
arm instruction set S3F441FX risc microcontroller 3- 76 format 5: hi-register operations/branch exchange 15 0 0 14 10 [2:0] destination register [5:3] source register [6] hi operand flag 2 [7] hi operand flag 1 [9:8] opcode 6 5 3 2 rd/hd 0 0 13 12 11 op rs/hs 0 0 0 9 8 7 h1 h2 figure 3-34. format 5 operation there are four sets of instructions in this group. the first three allow add, cmp and mov operations to be performed between lo and hi registers, or a pair of hi registers. the fourth, bx, allows a branch to be performed which may also be used to switch processor state. the thumb assembler syntax is shown in table 3-12. note in this group only cmp (op = 01) sets the cpsr condition codes. the action of h1= 0, h2 = 0 for op = 00 (add), op =01 (cmp) and op = 10 (mov) is undefined, and should not be used. table 3-12. summary of format 5 instructions op h1 h2 thumb assembler arm equivalent action 00 0 1 add rd, hs add rd, rd, hs add a register in the range 8-15 to a register in the range 0-7. 00 1 0 add hd, rs add hd, hd, rs add a register in the range 0-7 to a register in the range 8-15. 00 1 1 add hd, hs add hd, hd, hs add two registers in the range 8-15 01 0 1 cmp rd, hs cmp rd, hs compare a register in the range 0-7 with a register in the range 8-15. set the condition code flags on the result. 01 1 0 cmp hd, rs cmp hd, rs compare a register in the range 8-15 with a register in the range 0-7. set the condition code flags on the result.
S3F441FX risc microcontroller arm instruction s et 3- 77 table 3-12. summary of format 5 instructions (continued) op h1 h2 thumb assembler arm equivalent action 01 1 1 cmp hd, hs cmp hd, hs compare two registers in the range 8-15. set the condition code flags on the result. 10 0 1 mov rd, hs mov rd, hs move a value from a register in the range 8-15 to a register in the range 0- 7. 10 1 0 mov hd, rs mov hd, rs move a value from a register in the range 0-7 to a register in the range 8-15. 10 1 1 mov hd, hs mov hd, hs move a value between two registers in the range 8-15. 11 0 0 bx rs bx rs perform branch (plus optional state change) to address in a register in the range 0-7. 11 0 1 bx hs bx hs perform branch (plus optional state change) to address in a register in the range 8-15. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-12. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. the bx instruction bx performs a branch to a routine whose start address is specified in a lo or hi register. bit 0 of the address determines the processor state on entry to the routine: bit 0 = 0 causes the processor to enter arm state. bit 0 = 1 causes the processor to enter thumb state. note the action of h1 = 1 for this instruction is undefined, and should not be used.
arm instruction set S3F441FX risc microcontroller 3- 78 examples hi-register operations add pc, r5 ; pc := pc + r5 but don't set the condition codes. cmp r4, r12 ; set the condition codes o n the result of r4 - r12. mov r15, r14 ; move r14 (lr) into r15 (pc) ; but don't set the condition codes, ; eg. return from subroutine. branch and exchange ; switch from thumb to arm state. adr r1,outofthumb ; load address of outofthumb into r1. mov r11,r1 bx r11 ; transfer the contents of r11 into the pc. ; bit 0 of r11 determines whether ; arm or thumb state is entered, ie. arm state here. align code32 outofthumb ; now proce ssing arm instructions... using r15 as an operand if r15 is used as an operand, the value will be the address of the instruction + 4 with bit 0 cleared. executing a bx pc in thumb state from a non-word aligned address will result in unpredictable execution.
S3F441FX risc microcontroller arm instruction s et 3- 79 format 6: pc-relative load 15 0 0 14 10 [7:0] immediate value [10:8] destination register word 8 0 0 13 12 11 rd 0 0 8 7 figure 3-35. format 6 operation this instruction loads a word from an address specified as a 10-bit immediate offset from the pc. the thumb assembler syntax is shown below. table 3-13. summary of pc-relative load instruction thumb assembler arm equivalent action ldr rd, [pc, # imm] ldr rd, [r15, # imm] add unsigned offset (255 words, 1020 bytes) in imm to the current value of the pc. load the word from the resulting address into rd. note : the value specified by # imm is a full 10-bit address, but must always be word-aligned ( ie with bits 1:0 set to 0), since the assembler places # imm >> 2 in field word 8. the value of the pc will be 4 bytes greater than the address of this instruction, but bit 1 of the pc is forced to 0 to ensure it is word aligned.
arm instruction set S3F441FX risc microcontroller 3- 80 instruction cycle times all instructions in this format have an equivalent arm instruction. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples ldr r3,[pc,#844] ; load into r3 the word found at the ; address formed by adding 844 to pc. ; bit[1] of pc is forced to zero. ; note that the thumb opcode will contain ; 211 as the word8 value.
S3F441FX risc microcontroller arm instruction s et 3- 81 format 7: load/store with register offset [2:0] source/destination register [5:3] base register [8:6] offset register [10] byte/word flag 0 = transfer word quantity 1 = transfer byte quantity [11] load/store flag 0 = store to memory 1 = load from memory 15 0 0 14 10 6 5 3 2 rd 1 0 13 12 11 rb 1 l b 9 8 ro 0 figure 3-36. format 7
arm instruction set S3F441FX risc microcontroller 3- 82 operation these instructions transfer byte or word values between registers and memory. memory addresses are pre- indexed using an offset register in the range 0-7. the thumb assembler syntax is shown in table 3-14. table 3-14. summary of format 7 instructions l b thumb assembler arm equivalent action 0 0 str rd, [ rb, ro] str rd, [ rb, ro] pre-indexed word store: calculate the target address by adding together the value in rb and the value in ro. store the contents of rd at the address. 0 1 strb rd, [ rb, ro] strb rd, [ rb, ro] pre-indexed byte store: calculate the target address by adding together the value in rb and the value in ro. store the byte value in rd at the resulting address. 1 0 ldr rd, [ rb, ro] ldr rd, [ rb, ro] pre-indexed word load: calculate the source address by adding together the value in rb and the value in ro. load the contents of the address into rd. 1 1 ldrb rd, [ rb, ro] ldrb rd, [ rb, ro] pre-indexed byte load: calculate the source address by adding together the value in rb and the value in ro. load the byte value at the resulting address. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-14. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples str r3, [r2,r6] ; store word in r3 at the address ; formed by adding r6 to r2. ldrb r2, [r0,r7] ; load into r2 the byte found at ; the address formed by adding r7 to r0.
S3F441FX risc microcontroller arm instruction s et 3- 83 format 8: load/store sign-extended byte/half-word [2:0] destination register [5:3] base register [8:6] offset register [10] sign-extended flag 0 = operand not sing-extended 1 = operand sing-extended [11] h flag 15 0 0 14 10 6 5 3 2 rd 1 0 13 12 11 rb 1 h s 9 8 ro 1 figure 3-37. format 8 operation these instructions load optionally sign-extended bytes or half-words, and store half-words. the thumb assembler syntax is shown below. table 3-15. summary of format 8 instructions l b thumb assembler arm equivalent action 0 0 strh rd, [ rb, ro] strh rd, [ rb, ro] store half-word: add ro to base address in rb. store bits 0-15 of rd at the resulting address. 0 1 ldrh rd, [ rb, ro] ldrh rd, [ rb, ro] load half-word: add ro to base address in rb. load bits 0-15 of rd from the resulting address, and set bits 16-31 of rd to 0. 1 0 ldsb rd, [ rb, ro] ldrsb rd, [ rb, ro] load sign-extended byte: add ro to base address in rb. load bits 0-7 of rd from the resulting address, and set bits 8-31 of rd to bit 7. 1 1 ldsh rd, [ rb, ro] ldrsh rd, [ rb, ro] load sign-extended half-word: add ro to base address in rb. load bits 0-15 of rd from the resulting address, and set bits 16-31 of rd to bit 15.
arm instruction set S3F441FX risc microcontroller 3- 84 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-15. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples strh r4, [r3, r0] ; store the lower 16 bits of r4 at the ; address formed by adding r0 to r3. ldsb r2, [r7, r1] ; load into r2 the sign extended byte ; found at the address formed by adding r1 to r7. ldsh r3, [r4, r2] ; load into r3 the sign extended half-word ; found at the address formed by adding r2 to r4.
S3F441FX risc microcontroller arm instruction s et 3- 85 format 9: load/store with immediate offset [2:0] source/destination register [5:3] base register [10:6] offset register [11] load/store flag 0 = store to memory 1 = load from memory [12] byte/word flad 0 = transfer word quantity 1 = transfer byte quantity 15 0 0 14 10 6 5 3 2 rd 1 1 13 12 11 rb b l offset5 figure 3-38. format 9 operation these instructions transfer byte or word values between registers and memory using an immediate 5 or 7-bit offset. the thumb assembler syntax is shown in table 3-16. table 3-16. summary of format 9 instructions l b thumb assembler arm equivalent action 0 0 str rd, [ rb, # imm] str rd, [ rb, # imm] calculate the target address by adding together the value in rb and imm. store the contents of rd at the address. 1 0 ldr rd, [ rb, # imm] ldr rd, [ rb, # imm] calculate the source address by adding together the value in rb and imm. load rd from the address. 0 1 strb rd, [ rb, # imm] strb rd, [ rb, # imm] calculate the target address by adding together the value in rb and imm. store the byte value in rd at the address. 1 1 ldrb rd, [ rb, # imm] ldrb rd, [ rb, # imm] calculate source address by adding together the value in rb and imm. load the byte value at the address into rd. note : for word accesses (b = 0), the value specified by # imm is a full 7-bit address, but must be word-aligned ( ie with bits 1:0 set to 0), since the assembler places # imm >> 2 in the offset5 field.
arm instruction set S3F441FX risc microcontroller 3- 86 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-16. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples ldr r2, [r5,#116] ; load into r2 the word found at the ; address formed by adding 116 to r5. ; note that the thumb opcode will ; contain 29 as the offset5 value. strb r1, [r0,#13] ; store the lower 8 bits of r1 at the ; address formed by adding 13 to r0. ; note that the thumb opcode will ; contain 13 as the offset5 value.
S3F441FX risc microcontroller arm instruction s et 3- 87 format 10: load/store half-word [2:0] source/destination register [5:3] base register [10:6] immediate value [11] load/store flag 0 = store to memory 1 = load from memory 15 0 0 14 10 6 5 3 2 rd 1 0 13 12 11 rb 0 l offset5 figure 3-39. format 10 operation these instructions transfer half-word values between a lo register and memory. addresses are pre-indexed, using a 6-bit immediate value. the thumb assembler syntax is shown in table 3-17. table 3-17. half-word data transfer instructions l thumb assembler arm equivalent action 0 strh rd, [ rb, # imm] strh rd, [ rb, # imm] add # imm to base address in rb and store bits 0 - 15 of rd at the resulting address. 1 ldrh rd, [ rb, # imm] ldrh rd, [ rb, # imm] add # imm to base address in rb. load bits 0-15 from the resulting address into rd and set bits 16-31 to zero. note : # imm is a full 6-bit address but must be half-word-aligned ( ie with bit 0 set to 0) since the assembler places # imm >> 1 in the offset5 field.
arm instruction set S3F441FX risc microcontroller 3- 88 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-17. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples strh r6, [r1, #56] ; store the lower 16 bits of r4 at the address formed by ; adding 56 r1. note that the thumb opcode will contain ; 28 as the offset5 value. ldrh r4, [r7, #4] ; load into r4 the half-word found at the address formed by ; adding 4 to r7. note that the thumb opcode will contain ; 2 as the offset5 value.
S3F441FX risc microcontroller arm instruction s et 3- 89 format 11: sp-relative load/store [7:0] immediate value [10:8] destination register [11] load/store bit 0 = store to memory 1 = load from memory 15 0 1 14 10 0 0 13 12 11 word 8 1 l rd 7 8 figure 3-40. format 11 operation the instructions in this group perform an sp-relative load or store.the thumb assembler syntax is shown in the following table. table 3-18. sp-relative load/store instructions l thumb assembler arm equivalent action 0 str rd, [sp, # imm] str rd, [r13 # imm] add unsigned offset (255 words, 1020 bytes) in imm to the current value of the sp (r7). store the contents of rd at the resulting address. 1 ldr rd, [sp, # imm] ldr rd, [r13 # imm] add unsigned offset (255 words, 1020 bytes) in imm to the current value of the sp (r7). load the word from the resulting address into rd. note : the offset supplied in # imm is a full 10-bit address, but must always be word-aligned ( ie bits 1:0 set to 0), since the assembler places # imm >> 2 in the word8 field. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-18. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples str r4, [sp,#492] ; store the contents of r4 at the address ; formed by adding 492 to sp (r13). ; note that the thumb opcode will contain ; 123 as the word8 value.
arm instruction set S3F441FX risc microcontroller 3- 90 format 12: load address [7:0] 8-bit unsigned constant [10:8] destination register [11] source 0 = pc 1 = sp 15 0 1 14 10 0 1 13 12 11 word 8 0 sp rd 7 8 figure 3-41. format 12 operation these instructions calculate an address by adding an 10-bit constant to either the pc or the sp, and load the resulting address into a register. the thumb assembler syntax is shown in the following table. table 3-19. load address l thumb assembler arm equivalent action 0 add rd, pc, # imm add rd, r15, # imm add # imm to the current value of the program counter (pc) and load the result into rd. 1 add rd, sp, # imm add rd, r13, # imm add # imm to the current value of the stack pointer (sp) and load the result into rd. note : the value specified by # imm is a full 10-bit value, but this must be word-aligned ( ie with bits 1:0 set to 0) since the assembler places # imm >> 2 in field word 8. where the pc is used as the source register (sp = 0), bit 1 of the pc is always read as 0. the value of the pc will be 4 bytes greater than the address of the instruction before bit 1 is forced to 0. the cpsr condition codes are unaffected by these instructions.
S3F441FX risc microcontroller arm instruction s et 3- 91 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-19. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples add r2, pc, #572 ; r2 := pc + 572, but don't set the ; condition codes. bit[1] of pc is forced to zero. ; note that the thumb opcode will ; contain 143 as the word8 value. add r6, sp, #212 ; r6 := sp (r13) + 212, but don't ; set the condition codes. ; note that the thumb opcode will ; contain 53 as the word 8 value.
arm instruction set S3F441FX risc microcontroller 3- 92 format 13: add offset to stack pointer [6:0] 7-bit immediate value [7] sign flag 0 = offset is positive 1 = offset is negative 15 0 1 14 10 0 1 13 12 11 sword 7 1 0 0 7 8 9 6 0 0 s figure 3-42. format 13 operation this instruction adds a 9-bit signed constant to the stack pointer. the following table shows the thumb assembler syntax. table 3-20. the add sp instruction l thumb assembler arm equivalent action 0 add sp, # imm add r13, r13, # imm add # imm to the stack pointer (sp). 1 add sp, # - imm sub r13, r13, # imm add #- imm to the stack pointer (sp). note: the offset specified by # imm can be up to -/+ 508, but must be word-aligned ( ie with bits 1:0 set to 0) since the assembler converts # imm to an 8-bit sign + magnitude number before placing it in field sword7. the condition codes are not set by this instruction. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-20. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples add sp, #268 ; sp (r13) := sp + 268, but don't set the condition codes. ; note that the thumb opcode will ; contain 67 as the word7 value and s=0. add sp, #-104 ; sp (r13) := sp - 104, but don't set the condition codes. ; note that the thumb opcode will contain ; 26 as the word7 value and s=1.
S3F441FX risc microcontroller arm instruction s et 3- 93 format 14: push/pop registers [7:0] register list [8] pc/lr bit 0 = do not store lr/load pc 1 = store lr/load pc [11] load/store bit 0 = store to memory 1 = load from memory 15 0 1 14 10 0 1 13 12 11 rlist 1 l 0 7 8 9 1 r figure 3-43. format 14 operation the instructions in this group allow registers 0-7 and optionally lr to be pushed onto the stack, and registers 0-7 and optionally pc to be popped off the stack. the thumb assembler syntax is shown in table 3-21. note the stack is always assumed to be full descending. table 3-21. push and pop instructions l b thumb assembler arm equivalent action 0 0 push { rlist } stmdb r13!, { rlist } push the registers specified by rlist onto the stack. update the stack pointer. 0 1 push { rlist, lr } stmdb r13!, { rlist, r14 } push the link register and the registers specified by rlist (if any) onto the stack. update the stack pointer. 1 0 pop { rlist } ldmia r13!, { rlist } pop values off the stack into the registers specified by rlist. update the stack pointer. 1 1 pop { rlist, pc } ldmia r13!, { rlist, r15} pop values off the stack and load into the registers specified by rlist. pop the pc off the stack. update the stack pointer.
arm instruction set S3F441FX risc microcontroller 3- 94 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-21. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples push {r0-r4,lr} ; store r0,r1,r2,r3,r4 and r14 (lr) at ; the stack pointed to by r13 (sp) and update r13. ; useful at start of a sub-routine to ; save workspace and return address. pop {r2,r6,pc} ; load r2,r6 and r15 (pc) from the stack ; pointed to by r13 (sp) and update r13. ; useful to restore workspace and return from sub-routine.
S3F441FX risc microcontroller arm instruction s et 3- 95 format 15: multiple load/store [7:0] register list [10:8] base register [11] load/store bit 0 = store to memory 1 = load from memory 15 0 1 14 10 1 0 13 12 11 rlist 0 l 7 8 rb figure 3-44. format 15 operation these instructions allow multiple loading and storing of lo registers. the thumb assembler syntax is shown in the following table. table 3-22. the multiple load/store instructions l thumb assembler arm equivalent action 0 stmia rb!, { rlist } stmia rb!, { rlist } store the registers specified by rlist, starting at the base address in rb. write back the new base address. 1 ldmia rb!, { rlist } ldmia rb!, { rlist } load the registers specified by rlist, starting at the base address in rb. write back the new base address. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-22. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples stmia r0!, {r3-r7} ; store the contents of registers r3-r7 ; starting at the address specified in ; r0, incrementing the addresses for each word. ; write back the updated value of r0.
arm instruction set S3F441FX risc microcontroller 3- 96 format 16: conditional branch [7:0] 8-bit signed immediate [11:8] condition 15 0 1 14 1 0 13 12 11 soffset 8 1 7 8 cond figure 3-45. format 16 operation the instructions in this group all perform a conditional branch depending on the state of the cpsr condition codes. the branch offset must take account of the prefetch operation, which causes the pc to be 1 word (4 bytes) ahead of the current instruction. the thumb assembler syntax is shown in the following table. table 3-23. the conditional branch instructions l thumb assembler arm equivalent action 0000 beq label beq label branch if z set (equal) 0001 bne label bne label branch if z clear (not equal) 0010 bcs label bcs label branch if c set (unsigned higher or same) 0011 bcc label bcc label branch if c clear (unsigned lower) 0100 bmi label bmi label branch if n set (negative) 0101 bpl label bpl label branch if n clear (positive or zero) 0110 bvs label bvs label branch if v set (overflow) 0111 bvc label bvc label branch if v clear (no overflow) 1000 bhi label bhi label branch if c set and z clear (unsigned higher) 1001 bls label bls label branch if c clear or z set (unsigned lower or same)
S3F441FX risc microcontroller arm instruction s et 3- 97 table 3-23. the conditional branch instructions (continued) l thumb assembler arm equivalent action 1001 bls label bls label branch if c clear or z set (unsigned lower or same) 1010 bge label bge label branch if n set and v set, or n clear and v clear (greater or equal) 1011 blt label blt label branch if n set and v clear, or n clear and v set (less than) 1100 bgt label bgt label branch if z clear, and either n set and v set or n clear and v clear (greater than) 1101 ble label ble label branch if z set, or n set and v clear, or n clear and v set (less than or equal) notes: 1. while label specifies a full 9-bit two's complement address, this must always be half-word-aligned ( ie with bit 0 set to 0) since the assembler actually places label >> 1 in field soffset8. 2. cond = 1110 is undefined, and should not be used. cond = 1111 creates the swi instruction: see . instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-23. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples cmp r0, #45 ; branch to over-if r0 > 45. bgt over ; note that the thumb opcode will contain ; the number of half-words to offset. over ; must be half-word aligned.
arm instruction set S3F441FX risc microcontroller 3- 98 format 17: software interrupt [7:0] comment field 15 0 1 14 1 0 13 12 11 value 8 1 7 8 10 9 1 1 1 1 figure 3-46. format 17 operation the swi instruction performs a software interrupt. on taking the swi, the processor switches into arm state and enters supervisor (svc) mode. the thumb assembler syntax for this instruction is shown below. table 3-24. the swi instruction thumb assembler arm equivalent action swi value 8 swi value 8 perform software interrupt: move the address of the next instruction into lr, move cpsr to spsr, load the swi vector address (0x8) into the pc. switch to arm state and enter svc mode. note: value8 is used solely by the swi handler; it is ignored by the processor. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-24. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples swi 18 ; take the software interrupt exception. ; enter supervisor mode with 18 as the ; requested swi number.
S3F441FX risc microcontroller arm instruction s et 3- 99 format 18: unconditional branch [10:0] immediate value 15 0 1 14 1 1 13 12 11 offset11 0 10 0 figure 3-47. format 18 operation this instruction performs a pc-relative branch. the thumb assembler syntax is shown below. the branch offset must take account of the prefetch operation, which causes the pc to be 1 word (4 bytes) ahead of the current instruction. table 3-25. summary of branch instruction thumb assembler arm equivalent action b label bal label (half-word offset) branch pc relative +/- offset11 << 1, where label is pc +/- 2048 bytes. note: the address specified by label is a full 12-bit two's complement address, but must always be half-word aligned ( ie bit 0 set to 0), since the assembler places label >> 1 in the offset11 field. examples here b here ; branch onto itself. assembles to 0xe7fe. ; (note effect of pc offset). b jimmy ; branch to 'jimmy'. ; note that the thumb opcode will contain the number of ; half-words to offset. jimmy ; must be half-word aligned.
arm instruction set S3F441FX risc microcontroller 3- 100 format 19: long branch with link [10:0] long branch and link offset high/low [11] low/high offset bit 0 = offset high 1 = offset low 15 0 1 14 1 1 13 12 11 offset 1 10 h figure 3-48. format 19 operation this format specifies a long branch with link. the assembler splits the 23-bit two's complement half-word offset specifed by the label into two 11-bit halves, ignoring bit 0 (which must be 0), and creates two thumb instructions. instruction 1 (h = 0) in the first instruction the offset field contains the upper 11 bits of the target address. this is shifted left by 12 bits and added to the current pc address. the resulting address is placed in lr. instruction 2 (h =1) in the second instruction the offset field contains an 11-bit representation lower half of the target address. this is shifted left by 1 bit and added to lr. lr, which now contains the full 23-bit address, is placed in pc, the address of the instruction following the bl is placed in lr and bit 0 of lr is set. the branch offset must take account of the prefetch operation, which causes the pc to be 1 word (4 bytes) ahead of the current instruction
S3F441FX risc microcontroller arm instruction s et 3- 101 instruction cycle times this instruction format does not have an equivalent arm instruction. table 3-26. the bl instruction l thumb assembler arm equivalent action 0 bl label none lr := pc + offsethigh << 12 1 temp := next instruction address pc := lr + offsetlow << 1 lr := temp | 1 examples bl faraway ; unconditionally branch to 'faraway' next ; and place following instruction ; address, ie "next", in r14,the link ; register and set bit 0 of lr high. ; note that the thumb opcodes will ; contain the number of half-words to offset. faraway ; must be half-word aligned.
arm instruction set S3F441FX risc microcontroller 3- 102 instruction set examples the following examples show ways in which the thumb instructions may be used to generate small and efficient code. each example also shows the arm equivalent so these may be compared. multiplication by a constant using shifts and adds the following shows code to multiply by various constants using 1, 2 or 3 thumb instructions alongside the arm equivalents. for other constants it is generally better to use the built-in mul instruction rather than using a sequence of 4 or more instructions. thumb arm 1. multiplication by 2^n (1,2,4,8,...) lsl ra, rb, lsl #n ; mov ra, rb, lsl #n 2. multiplication by 2^n+1 (3,5,9,17,...) lsl rt, rb, #n ; add ra, rb, rb, lsl #n add ra, rt, rb 3. multiplication by 2^n-1 (3,7,15,...) lsl rt, rb, #n ; rsb ra, rb, rb, lsl #n sub ra, rt, rb 4. multiplication by -2^n (-2, -4, -8, ...) lsl ra, rb, #n ; mov ra, rb, lsl #n mvn ra, ra ; rsb ra, ra, #0 5. multiplication by -2^n-1 (-3, -7, -15, ...) lsl rt, rb, #n ; sub ra, rb, rb, lsl #n sub ra, rb, rt multiplication by any c = {2^n+1, 2^n-1, -2^n or -2^n-1} * 2^n effectively this is any of the multiplications in 2 to 5 followed by a final shift. this allows the following additional constants to be multiplied. 6, 10, 12, 14, 18, 20, 24, 28, 30, 34, 36, 40, 48, 56, 60, 62 ..... (2..5) ; (2..5) lsl ra, ra, #n ; mov ra, ra, lsl #n
S3F441FX risc microcontroller arm instruction s et 3- 103 general purpose signed divide this example shows a general purpose signed divide and remainder routine in both thumb and arm code. thumb code ; signed_divide ; signed divide of r1 by r0: returns quotient in r0, ; remainder in r1 ;get abs value of r0 into r3 asr r2, r0, #31 ; get 0 or -1 in r2 depending on sign of r0 eor r0, r2 ; eor with -1 (0 ffffffff) if negative sub r3, r0, r2 ; and add 1 (sub -1) to get abs value ;sub always sets flag so go & report division by 0 if necessary beq divide_by_zero ;get abs value of r1 by xoring with 0xffffffff and adding 1 if negative asr r0, r1, #31 ; get 0 or -1 in r3 depending on sign of r1 eor r1, r0 ; eor with -1 (0 ffffffff) if negative sub r1, r0 ; and add 1 (sub -1) to get abs value ;save signs (0 or -1 in r0 & r2) for later use in determining ; sign of quotient & remainder. push {r0, r2} ;justification, shift 1 bit at a time until divisor (r0 value) ; is just <= than dividend (r1 value). to do this shift dividend ; right by 1 and stop as soon as shifted value becomes >. lsr r0, r 1, #1 mov r2, r3 b %ft0 just_l lsl r2, #1 0 cmp r2, r0 bls just_l mov r0, #0 ; set accumulator to 0 b %ft0 ; branch into division loop div_l lsr r2, #1 0 cmp r1, r2 ; test subtract bcc %ft0 sub r1, r2 ; if successful do a real subtract 0 adc r0, r0 ; shift result and add 1 if subtract succeeded cmp r2, r3 ; terminate when r2 == r3 ( ie we have just bne div_l ; tested subtracting the 'ones' value).
arm instruction set S3F441FX risc microcontroller 3- 104 now fixup the signs of the quotient (r0) and remainder (r1) pop {r2, r3} ; get dividend/divisor si gns back eor r3, r2 ; result sign eor r0, r3 ; negate if result sign = - 1 sub r0, r3 eor r1, r2 ; negate remainder if dividend sign = - 1 sub r1, r2 mov pc, lr arm code signed_divide ; effectively zero a4 as top bit will be shifted out later ands a4, a1, #&80000000 rsbmi a1, a1, #0 eors ip, a4, a2, asr #32 ; ip bit 31 = sign of result ; ip bit 30 = sign of a2 rsbcs a2, a2, #0 ;central part is identical code to udiv (without mov a4, #0 which comes for free as part of signed entry sequence) movs a3, a1 beq divide_by_zero just_l ; justification stage shifts 1 bit at a time cmp a3, a2, lsr #1 movls a3, a3, lsl #1 ; nb: lsl #1 is always ok if ls succeeds blo s_loop div_l cmp a2, a3 adc a4, a4, a4 subcs a2, a2, a3 teq a3, a1 movne a3, a3, lsr #1 bne s_loop2 mov a1, a4 movs ip, ip, asl #1 rsbcs a1, a1, #0 rsbmi a2, a2, #0 mov pc, lr
S3F441FX risc microcontroller arm instruction s et 3- 105 division by a constant division by a constant can often be performed by a short fixed sequence of shifts, adds and subtracts. here is an example of a divide by 10 routine based on the algorithm in the arm cookbook in both thumb and arm code. thumb code udiv10 ; take argument in a1 returns quotient in a1, ; remainder in a2 mov a2, a1 lsr a3, a1, #2 sub a1, a3 lsr a3, a1, #4 add a1, a3 lsr a3, a1, #8 add a1, a3 lsr a3, a1, #16 add a1, a3 lsr a1, #3 asl a3, a1, #2 add a3, a1 asl a3, #1 sub a2, a3 cmp a2, #10 blt %ft0 add a1, #1 sub a2, #10 0 mov pc, lr arm code udiv10 ; take argument in a1 returns quotient in a1, ; remainder in a2 sub a2, a1, #10 sub a1, a1, a1, lsr #2 add a1, a1, a1, lsr #4 add a1, a1, a1, lsr #8 add a1, a1, a1, lsr #16 mov a1, a1, lsr #3 add a3, a1, a1, asl #2 subs a2, a2, a3, asl #1 addpl a1, a1, #1 addmi a2, a2, #10 mov pc, lr
arm instruction set S3F441FX risc microcontroller 3- 106 notes
S3F441FX risc microcontroller i/o ports 4- 1 4 i/o ports overview S3F441FX has 16 general input/output ports. ? seven ports are dedicated to being i/o ports only(gpio[6:0] ) ? nine ports are shared with other functional pins (multiplexed i/o ports :gpio[15:7] ) ? three external i nterrupt input or output pins each port can be easily configured by the software to meet various system configuration and design requirements. the cpu accesses i/o ports by directly writing or reading port register addresses. for this reason, special i/o instructions are not needed. table 4-1. S3F441FX port configuration overview port configuration options programmability 0 general c-mos push-pull i/o port with pull-up resistor port 0 consists of gpio[7:0]. gpio7 is multiplexed with tin. bit programmable 1 general c-mos push-pull i/o port with pull-up resistor port 1 consists of gpio[15:8]. gpio[15:8] are multiplexed with rxd,txd and a[17:12]. bit programmable 2 external interrupt input or output port bit programmable
i/o ports S3F441FX risc microcontroller 4- 2 port data registers table 4-2. port data register summary register name mnemonic offset reset value r/w port 0 data register p0 0xb000 xxh r/w port 1 data register p1 0xb001 xxh r/w port 2 data register p2 0xb002 xxh r/w port control registers table table 4-3. port control register summary register name mnemonic addr reset value r/w port 0 control register p0con 0xb010 00h r/w port 0 pull-up register p0pur 0xb015 ffh r/w port 1 control register p1con 0xb012 0000h r/w port 1 pull-up/down register p1pudr 0xb016 ffh r/w port 2 control register p2con 0xb014 0h r/w port 2 pull-up register p2pur 0xb017 7h r/w port 2 external interrupt control register eintcon 0xb018 0h r/w port 2 external interrupt mode register eintmod 0xb01a 00h r/w
S3F441FX risc microcontroller i/o ports 4- 3 table 4-4. port 0 control register name bit description p0con 0 setting the gpio[0] bit of port 0. 0 : c-mos input mode 1 : c-mos push-pull output mode 1 setting the gpio[1] bit of port 0. 0 : c-mos input mode 1 : c-mos push-pull output mode 2 setting the gpio[2] bit of port 0. 0 : c-mos input mode 1 : c-mos push-pull output mode 3 setting the gpio[3] bit of port 0. 0 : c-mos input mode 1 : c-mos push-pull output mode 4 setting the gpio[4] bit of port 0. 0 : c-mos input mode 1 : c-mos push-pull output mode 5 setting the gpio[5] bit of port 0. 0 : c-mos input mode 1 : c-mos push-pull output mode 6 setting the gpio[6] bit of port 0. 0 : c-mos input mode 1 : c-mos push-pull output mode 7 setting the gpio[7] bit of port 0. 0 : tin / c-mos input mode 1 : c-mos push-pull output mode p0pur 7-0 setting the gpio[7:0] pull-up resistor of port 0. 0 : disable pull-up resistor 1 : enable pull-up resistor
i/o ports S3F441FX risc microcontroller 4- 4 table 4-5. port 1 control register name bit description p1con 1:0 setting the gpio[8] bit of port 1. 00 : c-mos input mode 01 : c-mos push-pull output mode 10 : a12 3:2 setting the gpio[9] bit of port 1. 00 : c-mos input mode 01 : c-mos push-pull output mode 10 : a13 5:4 setting the gpio[10] bit of port 1. 00 : c-mos input mode 01 : c-mos push-pull output mode 10 : a14 7:6 setting the gpio[11] bit of port 1. 00 : c-mos input mode 01 : c-mos push-pull output mode 10 : a15 9:8 setting the gpio[12] bit of port 1. 00 : c-mos input mode 01 : c-mos push-pull output mode 10 : a16 11:10 setting the gpio[13] bit of port 1. 00 : c-mos input mode 01 : c-mos push-pull output mode 10 : a17 13:12 setting the gpio[14] bit of port 1. 00 : c-mos input mode 01 : c-mos push-pull output mode 10 : txd 15:14 setting the gpio[15] bit of port 1. 00 : rxd / c-mos input mode 01 : c-mos push-pull output mode p1pudr 5-0 setting the gpio[13:8] pull-down resistor of port 1. 0 : disable pull-down resistor 1 : enable pull-down resistor (when p1 is set as an address line, the pull-down resistor is automatically disabled.) 7-6 setting the gpio[15:14] pull-up resistor of port 1. 0 : disable pull-up resistor 1 : enable pull-up resistor
S3F441FX risc microcontroller i/o ports 4- 5 table 4-6. port2 control register name bit description p2con 2-0 setting the eint[2:0] bit of port 2. 0 : input or external interrupt input(eint2:0) 1 : c-mos push-pull output mode p2pur 2-0 setting the eint[2:0] pull-up resistor of port 2. 0 : disable pull-up resistor 1 : enable pull-up resistor eintmod 1,0 setting the external interrupt mode of eint0 00 : falling edge interrupt enable 01 : rising edge interrupt enable 10 : high level interrupt enable 11 : low level interrupt enable 3,2 setting the external interrupt mode of eint1 00 : falling edge interrupt enable 01 : rising edge interrupt enable 10 : high level interrupt enable 11 : low level interrupt enable 5,4 setting the external interrupt mode of eint2 00 : falling edge interrupt enable 01 : rising edge interrupt enable 10 : high level interrupt enable 11 : low level interrupt enable eintcon 2-0 setting the eint[2:0] interrupt enable 0 : disable external interrupt 1 : enable external interrupt
S3F441FX risc microcontroller basic/wat chdog timer 5- 1 5 basic/watchdog timer overview the S3F441FX has an internal basic timer/watch-dog timer. this timer can be used to resume controller operation when it has been disturbed due to noise or other kinds of system error or malfunctions. to configure the watch-dog timer, the overflow signal from the 8-bit basic timer should be fed to the clock input of the 3-bit watch-dog timer, as shown in figure below. user can enable or disable the watch-dog by software, i.e., by controlling the configuration in btcon register. if the user does not want to configure the watch-dog timer, the 8-bit basic timer can be used as a normal interval timer to request interrupt services. it also can signal the end of the required oscillation interval after a reset or a stop mode release. for example, the basic timer can give the overflow signal to necessary logic blocks after a reset or release from stop mode. in this case, the overflow signal from basic timer may mean that there is a stable clock from an external oscillator circuit. clock div fin/2 9 fin/2 11 fin/2 12 fin/2 13 extclk 8-bit basic counter (read only) 3-bit wdt nreset btcon.3-.2 cpu start intpend intmask ovf btcon.0 btint wdt control register (write 10100101b to disable) btcon.1 reset stop clear reset, stop, idle clear figure 5-1. watch-dog timer block diagram
basic/watchdog timer S3F441FX risc micr ocontroller 5- 2 basic timer counter register the basic timer counter register, btcnt(offset address : 0xa007), is used to specify the time out duration, and is a free-running 8-bit counter. the table below should be kept as reference for determining the duration of timer. this is the case when the external clock is 20mhz. register offset address r/w description reset value btcnt 0xa007 r basic timer count register 00h table 5-1. basic timer counter setting (at extclk = 20 mhz) btcon.3 btcon.2 clock source resolution interval time max. interval 0 0 extclk/2 13 409.6 m s 2 13 / extclk 2 8 104.86 ms 0 1 extclk /2 12 204.8 m s 2 12 / extclk 2 8 52.43 ms 1 0 extclk /2 11 102.4 m s 2 11 / extcl:k 2 8 26.21 ms 1 1 extclk /2 9 25.6 m s 2 9 / extclk 2 8 6.55 ms external oscillation stabilization time after stop or reset in figure 5-1, the cpu start signal after reset or stop is activated just after the 8-bit basic timer bit 4 is set to 1. so, there is delay time before cpu is started after reset or stop is released. this delay time may be used for the oscillation time of an external clock source. this delay time is calculated as in table 5-2. table 5-2. the delay time before cpu time start (at extclk = 20 mhz) btcon.3 btcon.2 clock source wdt interval delay time 0 0 extclk/2 13 2 13 / extclk 2 4 6.55 ms 0 1 extclk /2 12 2 12 / extclk 2 4 3.28 ms 1 0 extclk /2 11 2 11 / extclk 2 4 1.64 ms 1 1 extclk /2 9 2 9 / extclk 2 4 0.41 ms watch dog timer counter the watch dog timer counter register, wtcnt, is used to specify the time out duration and is a free-running 3-bit counter. to enable watch-dog timer, user should write the data in btcon[15:8] register except 0xa5, which will disable the watch-dog timer. after writing a value in the btcon[15:8] register the system will reset if there is an overflow. table 5-3. watch dog timer counter setting (at extclk = 20 mhz) btcon.3 btcon.2 clock source resolution wdt interval interval time 0 0 extclk/2 13 409.6 m s 2 13 / extclk 2 8 2 3 838.86 ms 0 1 extclk /2 12 204.8 m s 2 12 / extclk 2 8 2 3 419.43 ms 1 0 extclk /2 11 102.4 m s 2 11 / extclk 2 8 2 3 209.72 ms 1 1 extclk /2 9 25.6 m s 2 9 / extclk 2 8 2 3 52.43 ms
S3F441FX risc microcontroller basic/wat chdog timer 5- 3 basic timer control register the basic timer control register, btcon, contains watch-dog counter enable bits, clock input setting bits, and counter clear bit. register offset address r/w description reset value btcon 0xa002 r/w basic timer control register 0000h the basic timer control register has the following bits: [0] wdt counter clear bit this bit clears the watch dog counter. when this bit is set, the watch-dog counter register will be cleared to zero.(synchronous reset) and this bit will be cleared automatically. [1] basic counter clear bit this bit clears the basic counter. when this bit is set, the basic timer counter register will be cleared to all zero.(synchronous reset) and this bit will be cleared automatically. [3:2] clock source select these bits select a clock source. 11b = extclk / 2 9 10b = extclk / 2 11 01b = extclk / 2 12 00b = extclk / 2 13 [15:8] watch dog timer enable these bits enable or disable the watch-dog timer counting. when these bits are {10100101b}, watch dog timer counter is stopped. the other value enable watch-dog timer counting, and reset the system if there is an overflow.
basic/watchdog timer S3F441FX risc micr ocontroller 5- 4 function description interval timer function the primary function of a basic timer is to measure the elapsed time intervals. the standard time interval is equal to 256 basic timer clock pulses. the content of the 8-bit counter register, btcnt, increases every time a clock signal corresponding to the btcon selected frequency is detected. the btcnt continues its counting until an overflow occurs, i.e., the content reaches 255. an overflow set on the bt interrupt pending flag, which signals elapse of the designated time interval. then, an interrupt request is generated; btcnt is cleared to all zero; and the counting continues from 00h, again. watchdog timer function the basic timer can also be used as a "watch-dog" timer to detect an unexpected program sequence, that is, a system or program operation error due to an external factor. for example, an external noise can create an this type of error in which the cpu is running an unexpected code sequence, i.e., malfunction of cpu. to recover the cpu from the unexpected sequence, the watch-dog timer should reset the cpu for malfunctions. but, during normal sequence, the instruction, which clears the watch-dog timer within a given period, should be executed at proper points in a program. if an instruction that clears the watch-dog timer is not executed within the specified period, meaning an overflow of the watch-dog timer, the reset signal should be generated and the system should be restarted with reset status. an operation of watch-dog timer is as follows: ? each time btcnt overflows, an overflow signal should be sent to the watch-dog timer counter, wdtcnt. ? if wdtcnt overflows, the system reset should be generated. a reset signal clears the btcon as #0000h. this value can enable the watch-dog timer because it is not 0xa5. during the normal operation, the application program should prevent the overflow. to do this, the wdtcnt value should be cleared (by writing a "1" to btcon.0) at regular intervals before the overflow occurs.
S3F441FX risc microcontroller timer mod ule 0,1,2,3,4,5 6- 1 6 timer module 0,1,2, 3,4,5 (16-bit timers) overview the S3F441FX has six 16 -bit timers:t0,t1,t2,t3,t4 and t5. the timers t0-t5 can operate in interval mode, in capture mode, or in match & overflow mode. the clock source for the timers can be utclk or tin. you can enable or disable the timers by setting the control bits in the corresponding timer mode register. the timers 0,1,2,3,4, and 5 have three operating modes. the user can select the mode by having the appropriate tncon setting: ? interval timer mode ? capture input mode with a rising or falling edge trigger at the input pin(tin, which is shared by timer0/1/2/3/4/5 ) ? match & overflow mode
timer module 0,1,2,3,4,5 S3F441FX risc microcontroller 6- 2 tncon.6 8-bit prescaler clear utclk tncon.7 mux 16-bit up counter (tncnt) 16-bit comparator timer n buffer register timer n data register (read/write) tncon.6 intpnd intmask tncon.5-.3 tin r clear data bus tnovf intpnd intmask tnint tncon.5-.3 data bus match signal tnclr tnovf timer n control register where, n = 0, 1, 2, 3, 4 and 5 match tncon.2 figure 6-1. 16-bit timer block diagram
S3F441FX risc microcontroller timer mod ule 0,1,2,3,4,5 6- 3 timer 0,1,2,3,4,5 control registers(t0con,t1con,t2con,t3con,t4con,t5con) users should have the configuration on the timer 0,1,2,3,4, and 5 control registers, i.e., tncon, to determine the following: ? select the timer n operating mode (interval timer mode, match & overflow mode, or capture mode) ? select the timer n input clock (utclk or tin) ? clear the timer n counter, tncon[6] ? enable/disable the timer clock, tncon[7] the intmask register can control whether the interrupt to cpu should be posted or not when the timer n reaches to the overflow point in the interval timer mode, match & overflow mode, or capture mode. the intpend register can store the interrupt pending bit if the corresponding interrupt is not serviced. after the service of interrupt, the s/w should clear the pending bit. during the system reset, tncon register is cleared to '00h', automatically, which is a default configuration on the timer. the default configuration is to have the interval timer mode and utclk as the timer input clock source . user can clear the timer n counter at any time during normal operation by writing a "1" to tncon[6]. interval mode operation in interval timer mode, a match signal is generated when the counter value reaches to the written value in the tn reference data register, tndata. the match signal can generate a timer n match interrupt ( tnint) and clear the counter value. utclk tncnt clock tncnt tnpre=3 99 100 0 1 the timer match interrupt will occur. note: if the prescaler value is n, the prescaler factor is n + 1. figure 6-2. interval mode example 1 ( tndata=100, tnpre=3, utclk is a timer source)
timer module 0,1,2,3,4,5 S3F441FX risc microcontroller 6- 4 tin tncnt 99 100 0 1 the timer match interrupt will occur figure 6-3. interval mode example 2 (tndata=100, tin is a timer source ) capture mode operation in capture mode, the timer performs the capturing operation, in which the current timer counter value in tncnt register is latched to the timer n data register( tndata) in synchronization with an external trigger. for every external trigger signal, the current timer counter value in tncnt register is latched to the timer n data register( tndata) and the capture interrupt is generated. by using this feature, the user can measure the time difference between the external trigger signals. if the tncnt overflows, the overflow interrupt will be sent to the cpu core. a valid edge detected at the capture input pin is used as the external trigger. when this overflow happens, the timer counter starts its counting from 0000h. match & overflow mode operation in match mode, the match signal is generated when the timer counter value( tncnt) is identical to the value of the timer n data register( tndata), which was written by s/w. however, the match signal does not clear the counter and can generate a match interrupt, only. it runs continuously, overflowing at ffffh, and then continues the increment from 0000h. when an overflow happens, an overflow interrupt is also generated.
S3F441FX risc microcontroller timer mod ule 0,1,2,3,4,5 6- 5 timer special registers timer control registers the timer control registers, t0con, t1con, t2con, t3con, t4con, and t5con are used to control the operations of the six 16-bit timers. register offset address r/w description reset value t0con 0x9003 r/w timer 0 control register 00h t1con 0x9013 r/w timer 1 control register 00h t2con 0x9023 r/w timer 2 control register 00h t3con 0x9033 r/w timer 3 control register 00h t4con 0x9043 r/w timer 4 control register 00h t5con 0x9053 r/w timer 5 control register 00h three timer mode registers have the following control settings: [2] clock source selection this bit determines which clock source should be used as a timer input clock for the corresponding timer. when this bit is 0, utclk should be used as the timer clock source of the corresponding timer. when 1, tin should be used. [5:3] timer mode selection this field determines the operation mode of the corresponding timer to be used( interval, match & overflow mode, and capture mode) when the user sets tncon[5:3] to 000b, the corresponding timer runs in the interval mode. when 001b, the corresponding timer runs in the match & overflow mode. when the user sets tncon[5:3] to 1xx, the corresponding timer runs in the capture mode. when 100b, the corresponding timer runs in the capture and the capturing will happen at the falling edge of external triggering signal (tin). when 101b, the corresponding timer runs in the capture mode with the capturing at the rising edge of external triggering signal (tin). when 110b, the corresponding timer runs in the capture mode with the capturing at both edges of the external triggering signal(tin). [6] counter clear bit this bit can clear the counter register( tncnt). when this bit is set the counter is cleared. also, this bit is cleared automatically [7] timer clock enable/disable user can enable or disable the timer clock by setting or clearing this bit. when tncon[7] is 1, the divided utclk will be asserted to the 16-bit up-counter through the mux. otherwise, the divided utclk will not be fed. however, tin will not be controlled by this bit. although tncon[7] is 0, the tin will make the counter count.
timer module 0,1,2,3,4,5 S3F441FX risc microcontroller 6- 6 [1:0] reserved to 00b [2] timer n input clock selection bits 0 = extclk 1 = tin [5:3] timer n operation mode selection bits 000 = interval mode 001 = match & overflow mode (match &ovf int can occur) 010 = reserved 011 = reserved 100 = capture mode (capture on falling edge, counter running, ovf can occur) 101 = capture mode (capture on rising edge, counter running, ovf can occur) 110 = capture mode (capture on rising or falling edge, counter running, ovf can occur) [6] timer n counter 0 = no 1 = clear the timer n counter (when write) [7] timer n input clock enable bit 0 = disable timer n input clock 1 = enable timer n input clock 7 6 2 5 4 3 0 1 figure 6-4. timer 0,1,2,3,4,5 control registers
S3F441FX risc microcontroller timer mod ule 0,1,2,3,4,5 6- 7 timer data registers the timer data registers, t0data, t1data, t2data, t3data, t4data and t5data, contain values that specify the time-out duration for each timer. the formula for calculating time-out duration is (timer data + 1) cycles. see figure 6-5 below. register offset address r/w description reset value t0data 0x9000 r/w timer 0 data register ffffh t1data 0x9010 r/w timer 1 data register ffffh t2data 0x9020 r/w timer 2 data register ffffh t3data 0x9030 r/w timer 3 data register ffffh t4data 0x9040 r/w timer 4 data register ffffh t5data 0x9050 r/w timer 5 data register ffffh [15:0] timer data value this field specifies the time-out period the corresponding timer. the time-out period is calculated as (timer data + 1) cycles. therefore, a maximum time-out period of 2 16 cycles is possible (when the timer data value is 0xffff). the minimum time-out period (2 cycles) is obtained by writing the value 0x0001h to the timer data register field. 15 0 timer data figure 6-5. timer data registers ( tndata)
timer module 0,1,2,3,4,5 S3F441FX risc microcontroller 6- 8 timer count registers the timer count registers, t0cnt, t1cnt, t2cnt, t3cnt, t4cnt and t5cnt, have values which provides the count value to the current timers 0,1,2,3,4, and 5 during normal operation, respectively (see figure 6-6). register offset address r/w description reset value t0cnt 0x9006 r timer 0 count register 0000h t1cnt 0x9016 r timer 1 count register 0000h t2cnt 0x9026 r timer 2 count register 0000h t3cnt 0x9036 r timer 3 count register 0000h t4cnt 0x9046 r timer 4 count register 0000h t5cnt 0x9056 r timer 5 count register 0000h [15:0] counting value this field specifies the time-out period the corresponding timer. the time-out period is calculated as (timer data + 1) cycles. therefore, a maximum time-out period of 2 16 cycles is possible (when the timer data value is 0xffff). the minimum time-out period (2 cycles) is obtained by writing the value 0x0001h to the timer data register field. 15 0 counting data figure 6-6. timer count registers ( tncnt)
S3F441FX risc microcontroller timer mod ule 0,1,2,3,4,5 6- 9 timer pre-scaler registers the timer pre- scaler registers, t0pre, t1pre, t2pre, t3pre, t4pre, and t5pre, have values which provide the pre- scaler values (the main clock should be divided by the pre- scaler factor, which is the timer input clock) to current timers 0/1/2/3/4/5 during normal operation, respectively(see figure 6-7). register offset address r/w description reset value t0pre 0x9002 r/w timer 0 pre- scaler register ffh t1pre 0x9012 r/w timer 1 pre- scaler register ffh t2pre 0x9022 r/w timer 2 pre- scaler register ffh t3pre 0x9032 r/w timer 3 pre- scaler register ffh t4pre 0x9042 r/w timer 4 pre- scaler register ffh t5pre 0x9052 r/w timer 5 pre- scaler register ffh [7:0] timer 0,1,2,3,4,5 prescaler value this field cotains the timer 0,1,2,3,4,5 prescaler value during normal timer operation. 7 0 prescaler data figure 6-7. timer pre- scaler registers ( tnpre) a pre- scaler register has an 8-bit pre- scaler value. if the pre- scaler value is n, the prescaler factor is n+1.
S3F441FX risc microcontroller uart 7- 1 7 uart overview the S3F441FX has an on-chip uart(universal asynchronous receiver/transmitter) block. the uart can be operated in the interrupt-based mode a uart has a programmable baud rate generator with rx and tx ports for uart communication, tx and rx shift registers, tx and rx buffer registers, tx and rx control blocks and control registers. in other words the uart in S3F441FX supports the programmable baud rate, simultaneous transmit/receive(full duplex mode), one or two stop bit insertion, 5-bit, 6-bit, 7-bit, or 8-bit data transmit/receive size, and parity checking capability. the baud rate generator can generate the suitable bit rate by dividing the mclk (cpu clock) or extclk. the bit rate is fully programmable by s/w with an appropriate clock division factor, the programmable baud generator can generate uart bit rates 1200, 2400, 4800, 9600, and so on. the transmitter and the receiver block have tx and rx data buffer registers, and a tx and a rx shift register, respectively. the transmission data should be written to the tx buffer register, then copied to the tx shift register, and shifted out through the transmit data pin( tx). the data to be received should be shifted in through the receive data pin(rx), and then copied from shift register to the rx buffer register whenever one data byte is received. the control unit provides the selection on uart operation mode and shows the status/interrupt generation of uart during operation. uart baud rate = source clock / ( 16 x ( divisor value + 1 ))
uart S3F441FX risc microcontroller 7- 2 tx control tx. buffer reg data bus tx. shift reg rx. shift reg rx. buffer reg data bus lcon/ucon/ussr data bus rx control interrupt control serial clock generator tx rx ck ck baud rate generater 16-bit prescaler status mclk utclk ubrdr data bus lcon.6 figure 7-1. uart block diagram
S3F441FX risc microcontroller uart 7- 3 infra-red mode the S3F441FX uart block can support the infra-red (ir)-based transmit and receive ( irda 1.0), which can be selected by setting the infra-red-mode bit in the line control register (lcon). the implementation of the mode is shown in figure 7-2. in irda mode, the transmitted bit data is slightly different from the normal transmitted bit data. in normal transmitted bit data, the high value(logic 1) will be maintained during one bit time if the bit data is 1. otherwise, the low value(logic 0) will be maintained during one bit time if the bit data is 0. in irda mode, however, the high value(logic 1) will be pulsed with the duty of 3/16 during one bit time if the bit data is 1. otherwise, the low value(logic 0) will be maintained during one bit time if the bit data is 0. similarly with tx case of irda mode, the bit data of rx has same bit shape as tx. in other words, the receiver should detect the 3/16 pulsed-duty signal when the bit data is 1. the normal operation of rx is as same as the that of tx in terms of bit shaping during one bit time. urat block txd rxd irs re ir tx encoder 0 1 1 0 ir rx decoder txd rxd f igure 7-2. infra-red mode
uart S3F441FX risc microcontroller 7- 4 uart special registers uart line control register the uart line control register, lcon, is used to control the uart. register offset address r/w description reset value lcon 0x5003 r/w uart line control register 00h [1:0] word length (wl) the two-bit word length value indicates the number of data bits to be transmitted or received per frame. the options are 5-bit, 6-bit, 7 -bit, and 8-bit. [2] number of stop bits lcon[2] specifies how many stop bits should be inserted to signal end-of-frame(eof). when it is 0, one bit signals the eof; when it is 1, two bits signal eof. [5:3] parity mode (pmd) the 3-bit parity mode value specifies how the parity generation and checking should be performed during uart transmit and receive operations. there are five options (see figure 7-3). [6] baud rate clock selection when lcon[6] is 0, the internal system clock (mclk) is selected as the baud rate generator clock source. when it is 1, utclk is selected as the baud rate generator clock source [7] infra-red mode this bit determines whether or not to use infra-red mode 0 = normal mode operation 1 = infra-red tx/rx mode
S3F441FX risc microcontroller uart 7- 5 [1:0] word-length per frame (wl) 00 = 5-bit 01 = 6-bit 10 = 7-bit 11 = 8-bit [2] number of stop bits at end of frame 0 = one stop bit per frame 1 = two stop bit per frame [5:3] parity mode 0xx = no parity bit in frame 100 = odd parity 101 = even parity 110 = parity forced/checked as 1 111 = parity forced/checked as 0 [6] baud rate clock selection 0 = internal clock source (mclk) 1 = utclk [7] infra-red mode selection 0 = normal mode operation 1 = infra-red tx/rx mode 7 6 2 5 4 3 0 1 pmd wl figure 7-3. uart line control register (lcon)
uart S3F441FX risc microcontroller 7- 6 uart control register the uart control register, ucon, is used to control the single-channel uart. register offset address r/w description reset value ucon 0x5007 r/w uart control register 00h [1:0] reserved to 01b these bits enable the uart to generate a receive interrupt. [2] rx status interrupt enable this bit enables the uart to generate an interrupt if an exception (break, frame error, parity error, or overrun error) occurs during a receive operation. when ucon[2] is set to 1, a receive status interrupt will be generated each time a rx exception occurs. when ucon[2] is 0, no receive status interrupt will be generated. [4:3] reserved to 01b these bits enable the uart to generate a transmit interrupt [5] reserved unknown value will be read. [6] send break setting ucon[6] causes the uart to send a break. the break is defined as giving the continuous low level signal on the transmit data output( tx port) of more than one frame transmission time. when the transmitter is empty (transmitter empty bit, ussr[7] = 1), the exact one-frame time can be obtained by using tbr & ussr registers. when ussr[7] is 1, write dummy data to the transmit buffer register(tbr). then poll the ussr[7] value. when it returns to 1, clear(reset) the send break bit, ucon[6]. [7] loopback bit setting ucon[7] causes the uart to enter into the loop-back mode. in loop-back mode, the transmit buffer register (tbr) is internally connected to the receive buffer register (rbr). this mode is provided for test purposes only.
S3F441FX risc microcontroller uart 7- 7 [1:0] reserve interrupt enable 00 = do not generate a receive interrupt 01 = generate a receive interrupt 10 = not used 10 = not used [2] receive status in interrupt enable 0 = do not generate receive status interrupt 1 = generate receive status interrupt [4:3] transmit interrupt enable 00 = do not generate a transmit interrupt 01 = generate a transmit interrupt 10 = not used 10 = not used [5] reserved (unknown value) [6] send break 0 = do not send break 1 = send break [7] loop break enable 0 = normal uart operating 1 = infra-red tx/rx mode 7 6 2 5 4 3 0 1 txm rxm figure 7-4. uart control register (ucon)
uart S3F441FX risc microcontroller 7- 8 uart status register the uart status register, ussr, is a read-only register that is used to monitor the status of serial i/o operations in the single-channel uart. register offset address r/w description reset value ussr 0x500b r uart status register c0h [0] overrun error ussr[0] is automatically set to 1 whenever an overrun error occurs during a serial data receive operation. if the receive status interrupt enable bit ucon[2] is 1, a receive status interrupt will be generated if an overrun error occurs. this bit is automatically cleared to 0 whenever the uart status register (ussr) is read. [1] parity error ussr[1] is automatically set to 1 whenever a parity error occurs during a serial data receive operation. if the receive status interrupt enable bit ucon[2] is 1, a receive status interrupt will be generated if a parity error occurs. this bit is automatically cleared to 0 whenever the uart status register (ussr) is read. [2] frame error ussr[2] is automatically set to 1 whenever a frame error occurs during a serial data receive operation. if the receive status interrupt enable bit ucon[2] is 1, a receive status interrupt will be generated if a frame error occurs. the frame error bit is automatically cleared to 0 whenever the uart status register (ussr) is read. [3] break interrupt ussr[3] is automatically set to 1 to indicate that a break signal has been received. if the receive status interrupt enable bit, ucon[2], is 1, a receive status interrupt will be generated if a break occurs. the break interrupt bit is automatically cleared to 0 when you read the uart status register. [4] ? ? [5] receive data ready ussr[5] is automatically set to 1 whenever the receive data buffer register (rbr) contains the valid data received over the serial port. the receive data can then be read from the rbr. when this bit is 0, the rbr does not contain valid data. [6] tx buffer register empty ussr[6] is automatically set to 1 when the transmit buffer register (tbr) does not contain valid data. in this case, the tbr can be written with the data to be transmitted. when this bit is 0, the tbr contains valid tx data that has not yet been copied to the transmit shift register. in this case, the tbr cannot be written with new tx data. [7] transmitter empty (t) ussr[7] is automatically set to 1 when the transmit buffer register has no valid data to be transmitted and when the tx shift register is empty. when the transmitter empty bit is 1, it indicates that it can now disable the transmitter function block if necessary.
S3F441FX risc microcontroller uart 7- 9 7 6 2 5 4 3 0 1 [0] overrun error 0 = no overrun error during receive 1 = overrun error (generate receive status interrupt if ucon[2] is 1.) [1] parity error 0 = no parity error during receive 1 = parity error (generate receive status interrupt if ucon[2] is 1.) [2] frame error 0 = no frame error during receive 1 = frame error (generate receive status interrupt if ucon[2] is 1.) [3] break interrupt 0 = no break receive 1 = break error (generate receive status interrupt if ucon[2] is 1.) [5] receive data ready 0 = no valid data in the receive buffer register 1 = valid data present in the receive buffer register (issue interrupt) [6] transmit holding register empty 0 = valid data present in transmit holding register (issue interrupt) 1 = no valid data in transmit holding register [7] transmitter empty 0 = transmitter not empty; tx in progress 1 = transmitter empty; no data for tx x figure 7-5. uart status register (ussr)
uart S3F441FX risc microcontroller 7- 10 uart transmit buffer register the uart transmit holding register, tbr, contains an 8-bit data value to be transmitted over the single-channel uart. register offset address r/w description reset value tbr 0x500f w serial transmit buffer register xxh [7:0] transmit data this field contains the data to be transmitted over the single-channel uart. when this register is written, the transmit buffer register empty bit in the status register, ussr[6], should be 1. this prevents overwriting the transmit data which may already be present in the tbr. whenever the tbr is written with a new value, the transmit register empty bit ussr[6] is automatically cleared to 0. 7 0 [7:0] transmit data for uart this field contains the data to be transmitted over the serial i/o interface. to avoid overwriting data that has not yet been transmitted, the transmit holding register empty bit, ussr[6], should be 1. writing a value to this register automatically clears ussr[6] to 0. transmit data figure 7-6. uart transmit buffer register (tbr) note: tx interrupt will be generated only when the tbr register is empty. so, if the tbr register has been empty and you enable the utxd interrupt using intmask register, the utxd interrupt will not be generated. therefore, to generate the utxd interrupt, the first character among the characters to be transmitted should be written into tbr register.
S3F441FX risc microcontroller uart 7- 11 uart receive buffer register the receive buffer register, rbr, contains an 8-bit field for received serial data. register offset address r/w description reset value rbr 0x5013 r serial receive buffer register xxh [7:0] receive data this field contains the data received over the single-channel uart. when this register is read, the receive data ready bit in the uart status register, ussr[5], should be 1. this can prevent the reading of invalid receive data which may already be present in the rbr. whenever the rbr is written with a new value, the receive data ready bit, ussr[5], is automatically cleared to 0. 7 0 [7:0] receive data for uart this field contains the data received over the serial i/o interface. to avoid reading invalid data, the receive data ready bit, ussr[5], should be 1. reading this register automatically clears the ussr[5] value to 0. receive data figure 7-7. uart receive buffer register (rbr)
uart S3F441FX risc microcontroller 7- 12 uart baud rate prescaler registers the value stored in the baud rate divisor register, ubrdr, is used to determine the serial tx/rx clock rate (baud rate) as follows: baud rate = source_clock / ((divisor value + 1) x 16) the source_clock is either mclk (the internal master clock) or utclk(the external uart & timer clock input) and it can be determined by setting the serial clock selection bit in the line control register, lcon[6]. register offset address r/w description reset value ubrdr 0x5016 r/w baud rate divisor register 0000h 15 0 [7:0] baud-rate divisor vaule this field contains the baud rate divisor value for corresponding sio channel. baud rate can be calculated as: baud rate = source_clock / ((divisor value + 1) x 16) baud-rate divisor note: the value of the baud-rate divisor should be from 0 to (2 16 -1) figure 7-8. uart baud rate divisor registers (ubrdr)
S3F441FX risc microcontroller interrupt controller 8- 1 8 interrupt controller overview the S3F441FX interrupt architecture has a total of 19 interrupt sources. interrupt request can be generated by the internal functional blocks as well as external pins(external interrupt request). the arm7tdmi core can recognize two kinds of interrupt: a normal interrupt request (irq) and a fast interrupt request (fiq). therefore, all S3F441FX interrupts should be categorized as either irq or fiq. the interrupt sources in S3F441FX can be serviced, delayed, or not be serviced by the combined configuration on the registers intmode, intpend, and intmask. in the normal interrupt mode, the interrupt mode(irq or fiq) determine the start address of corresponding interrupt request. in other words, the start address of interrupt service should be 0x1c or 0x18 if the mode is fiq or irq. after jumping to 0x1c or 0x18, the s/w should determine the real start address of the corresponding service address. ? interrupt mode register(intmode). defines the interrupt mode, irq or fiq, for each interrupt source. ? interrupt pending register(intpend). indicates that an interrupt request is pending. when a pending bit is set, the interrupt service routine can start whenever the i-flag or f-flag is cleared to 0, which means that the previous service was finished or arm7tdmi core is ready to accept other interrupts request during the service of previous interrupt request. the service routine should clear the corresponding pending bit by writing 0 when cpu is ready to accept other interrupt requests or when the cpu exits from the corresponding service routine, at least. because fiq interrupt has higher priority than irq, the fiq mode interrupt can be serviced before the complete service of irq mode interrupt. ? interrupt mask register(intmask). indicat es that the corresponding interrupt request is not allowable if the corresponding mask bit is 0. if an interrupt mask bit is 1, the interrupt request will be allowable, normally.
interrupt controller S3F441FX risc micr ocontroller 8- 2 intpend intmask intpend intmask intpend intmask intpend intmask global interrupt enable irq/fiq source source source source figure 8-1. S3F441FX interrupt structure
S3F441FX risc microcontroller interrupt controller 8- 3 interrupt sources the 19 interrupt sources in the S3F441FX interrupt structure are described, in brief, as follows: [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] eint2 external interrupt. eint1 external interrupt. eint0 external interrupt. basic timer interrupt. timer 5 match/capture interrupt. timer 5 overflow interrupt. timer 4 match/capture interrupt. timer 4 overflow interrupt. timer 3 match/capture interrupt. timer 3 overflow interrupt. timer 2 match/capture interrupt. timer 2 overflow interrupt. timer 1 match/capture interrupt. timer 1 overflow interrupt. timer 0 match/capture interrupt. timer 0 overflow interrupt. uart error. uart transmit interrupt. uart receive interrupt.
interrupt controller S3F441FX risc micr ocontroller 8- 4 interrupt controller special registers interrupt mode register bits in the interrupt mode register(intmode) determine the interrupt mode of the requested interrupt. there are two kinds of interrupt mode, irq and fiq mode. when the bit is set to 1, the corresponding interrupt service should be serviced by fiq(fast interrupt mode) in arm7tdmi. otherwise, the corresponding interrupt service should be serviced by irq(normal interrupt request) mode in arm7tdmi. register offset address r/w description reset value intmode 0xc000 r/w interrupt mode register 0: irq mode 1: fiq mode xxx0 0000h [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] eint2 external interrupt. eint1 external interrupt. eint0 external interrupt. basic timer interrupt. timer 5 match/capture interrupt. timer 5 overflow interrupt. timer 4 match/capture interrupt. timer 4 overflow interrupt. timer 3 match/capture interrupt. timer 3 overflow interrupt. timer 2 match/capture interrupt. timer 2 overflow interrupt. timer 1 match/capture interrupt. timer 1 overflow interrupt. timer 0 match/capture interrupt. timer 0 overflow interrupt. uart error. uart transmit interrupt. uart receive interrupt.
S3F441FX risc microcontroller interrupt controller 8- 5 interrupt pending register the interrupt pending register (intpend) has interrupt pending bits for each interrupt source. when an interrupt request is generated, the cpu will mask it if the i-flag or f-flag in the process status register ( psr) is set because of a previous interrupt. when a pending bit is set, the interrupt service routine can start if the i-flag or f- flag is cleared to 0, which means that the previous service was finished or arm7tdmi core is ready to accept other interrupt requests during the service of the previous interrupt request. the service routine should clear the corresponding pending bit by writing 0 when cpu is ready to accept another interrupt request, or when the cpu exits from the corresponding service routine, at least. because fiq interrupt has higher priority than irq, the fiq mode interrupt can be serviced before the complete service of irq mode interrupt even if the i-bit in psr is set to 1. in other words, the fiq mode interrupt request can't be pending, if the irq mode interrupt service is on processing. register offset address r/w description reset value intpend 0xc004 r/w interrupt pending register read 0: no interrupt has been requested 1: the corresponding interrupt source has asserted the interrupt request. write 0: clear the corresponding pending bit. 1: preserve the previous pending bit status. xxx0 0000h [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] eint2 external interrupt. eint1 external interrupt. eint0 external interrupt. basic timer interrupt. timer 5 match/capture interrupt. timer 5 overflow interrupt. timer 4 match/capture interrupt. timer 4 overflow interrupt. timer 3 match/capture interrupt. timer 3 overflow interrupt. timer 2 match/capture interrupt. timer 2 overflow interrupt. timer 1 match/capture interrupt. timer 1 overflow interrupt. timer 0 match/capture interrupt. timer 0 overflow interrupt. uart error. uart transmit interrupt. uart receive interrupt.
interrupt controller S3F441FX risc micr ocontroller 8- 6 interrupt mask register the interrupt mask register (intmask) has interrupt mask bits for each interrupt source. each of the interrupt mask register (intmask) corresponds to an interrupt source. when an interrupt source mask bit is 0, the cpu does not allow the corresponding interrupt request. if the mask bit is 1, the interrupt is serviced or pending upon request. register offset address r/w description reset value intmask 0xc008 r/w interrupt mask register 0: disable the corresponding interrupt. 1: enable the corresponding interrupt. xxx0 0000h [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] eint2 external interrupt. eint1 external interrupt. eint0 external interrupt. basic timer interrupt. timer 5 match/capture interrupt. timer 5 overflow interrupt. timer 4 match/capture interrupt. timer 4 overflow interrupt. timer 3 match/capture interrupt. timer 3 overflow interrupt. timer 2 match/capture interrupt. timer 2 overflow interrupt. timer 1 match/capture interrupt. timer 1 overflow interrupt. timer 0 match/capture interrupt. timer 0 overflow interrupt. uart error. uart transmit interrupt. uart receive interrupt.
S3F441FX risc microcontroller system ma nager 9- 1 9 system manager overview the S3F441FX system manager has the following functions: ? supports the big- endian mode. the internal system and the external memory are fixed as big- endian mode. ? memory controller for external memory/io as well as internal mem ory. ? programmable bank start and bank end addresses. ? programmable access time for memory/io access.
system manager s3f4 41fx risc microcontroller 9- 2 system manager registers the S3F441FX has the sfrs, special function registers, to keep the system control information of system manager as well as the configuration on peripherals. among sfrs, there are smrs (system manager register files), to configure the external memory maps such sram, rom and etc. by utilizing the smr, the user can specify the memory type, access cycles, required control signal timings, and memory bank location. the smr provides (or accepts) the control signals and addresses which are needed to access external devices during normal system operation. three registers control the memory banks the S3F441FX provides up to 32mbytes of address space and each bank provides up to 256kbytes of memory space because each bank can have 18 address pins. 0x00000000 0x0003ffff 0x00800000 0x0083ffff 0x00c00000 0x00c3ffff 0x01ff0000 0x01ff2000 0x01ffffff internal 256kb flash rom cs1 (external memory) cs2 (external memory) 8kb internal sram sfr figure 9-1. S3F441FX default memory map of the normal mode(in rom mode)
S3F441FX risc microcontroller system ma nager 9- 3 0x00000000 0x0003ffff 0x00800000 0x0083ffff 0x00c00000 0x01f3ffff 0x01ff0000 0x01ff2000 0x01ffffff cs0 (external 256kb flash rom) cs1 (external memory) cs2 (external memory) 8kb internal sram sfr 256kb internal flash rom 0x00c3ffff 0x01f00000 figure 9-2. S3F441FX default memory map of external rom mode the S3F441FX provides 32-mbyte memory space and an internal 25-bit system address bus. you can use any of the bank area addresses from 000_0000h to 1ff_ffffh in 1m byte address steps. each bank can be located anywhere in the 32-mbyte address space. however, the user should allocate the sfrs to the upper 64-kbyte address areas, 1ff0000h -1ffffffh. the configurable memory allocation in the S3F441FX is very effective in meeting user requirement. by manipulating the smrs, the user can easily allocate the memory area anywhere user desires and use the consecutively connected memory space without changing the h/w. for example, if the user wants to change the size of memory space from 1mbytes to 2 mbytes, the user can expand the memory space by changing the next pointer of the bank and bank end address. note: although the size of each bank may be more than 1m bytes, the physical bank size is max 256kbytes because the number of the address pins is 18 in total.
system manager s3f4 41fx risc microcontroller 9- 4 system register address configuration register (syscfg) the smrs (system manager registers) have the syscfg (system register address configuration register), which determines the start address (base point) of sfr (special function register) files. the syscfg has the start address of sfr. because the reset value of syscfg is 1ff1h, the syscfg is mapped to the virtual address 01ff 1000h. register offset address r/w description reset value syscfg 0x3000 r/w special function register to determine the start address 0x1ff1 [0] stall enable (st) when set to 1, stall operation is enabled 0 = disable; it is recommended for faster operation. 1 = enable; insert an internal wait inside the core logic when non-sequential memory accesses occur. [12:4] syscfg address (sfrs start address) (read_only) t hese bits are fixed to 1ffh and it means sfrs start address is 1ff0000h 31 15 16 12 start 0 4 2 3 1 se 0 0 0 13 14 00 0 figure 9-3. system register address configuration register (syscfg)
S3F441FX risc microcontroller system ma nager 9- 5 external memory control special registers memory control register 0, 1, 2 register offset address r/w description reset value memcon0 0x4000 r/w memory control register 0 (ncs0) 0800 3000h memcon1 0x4004 r/w memory control register 1 (ncs1) 0c08 3000h memcon2 0x4008 r/w memory control register 2 (ncs2) 100c 3000h [1:0] reserved reserved to 00b [4:2] tcos 000 = 0 cycles 001 = 1 cycles 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles 111 = not used [7:5] tacs 000 = 0 cycles 001 = 1 cycles 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles 111 = not used [10:8] tcoh 000 = 0 cycles 001 = 1 cycles 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles 111 = not used [13:11] tacc memory access time( tacc) 000 = disable bank 001 = 2 cycles 010 = 3 cycles 011 = 4 cycles 100 = 5 cycles 101 = 6 cycles 110 = 7 cycles 111 = not used if nwait is used, tacc 3 3 [15:14] reserved reserved to 00b [23:16] base address(ba) indicates bank start address. user can configure bank size by 1mb unit. if bank start address is 0x0100000, the base address(ba) field value of this bank should be 0x01. the available range is 0-0x1e. [31:24] end address(ea) indicates bank end address. if the end address of the bank is 0x0f3ffff, the end address(ea) field value of this bank should be 0x10( (0f3ffffh>>20) +1). the available range is 0x1-0x1f notes: 1. ncs0 can be used for another external device if the in-rom mode is selected by md[1:0]=00b. if the ncs0 area is overlapped with the internal flash memory, the internal flash rom will be read by cpu. 2. ncs0 will be used for boot rom if the external rom mode is selected by md[1:0]=01b.
system manager s3f4 41fx risc microcontroller 9- 6 mclk (cpu clock) addr ncsn noe nwe tacs tcos tacc tcoh figure 9-4. an example of S3F441FX ncsn timing diagram
S3F441FX risc microcontroller internal flash rom 10- 1 10 internal flash rom overview the S3F441FX has an on-chip flash rom, internally. for writing the data in flash rom, the user can access the flash rom by a program or the external serial interface. because of the full feature of nor flash memory, user can program the data in any address and in any time. the size of embedded flash memory in S3F441FX is 256k- byte and it has the following features : ? tool program mode (apply v dd ?12.5 v externally and the dedicated serial interface) ? user program mode (use the internal high voltage generator) ? protection mode: hardware protection, read protection and ld protection the S3F441FX has 6 pins used for flash rom writer to read/write/erase the flash memory (v dd , v ss , reset, vpp , sdat, sclk ), which is the programming by tool program mode. these six pins are multiplexed with other functional pins. when the S3F441FX is in v pp (md1) = v dd ?12.5 v (internal flash rom test mode) & reset (nreset) = l, these six pins can be used for flash programming in tool program mode.
internal flash rom S3F441FX risc microcontroller 10- 2 programming modes the S3F441FX flash memory control block supports two kinds of program mode: ? tool program mode ? user program mode flash rom configuration the 256kb flash rom consists of 512 sectors. each sector consists of 512 bytes. so, the total size of flash rom is 512 x 512 bytes (256kb). user can erase the flash memory a sector unit at a time and write the data into the flash memory word (4 bytes) unit at a time. additionally, there is the option sector, which is different from 256kb memory cell. this optional sector consists of smart option bits and protection option bits. these bits control the protection features. these bits can be read only by the fsoread/fporead register. the smart option bits are mapped to the address of 0xe38(4bytes). the protection option bits are also mapped to the address of 0xe3c (4 bytes). address alignment to set an address value in fmaddr register, abide by the following rules. ? sector erase when erasing a sector, the low 9-bit address (fmaddr[8:0]) should be 000000000b because the size of a sector is 512 bytes. ? program when programming the flash rom, the lower 2-bit (fmaddr[1:0]) should be 00b because data should be written to the flash rom by a word unit (4 bytes). note: in the tool program mode, the low 2-bit address also should be 00b. user program mode the user program mode for flash memory programming and sector erasing uses the internal high voltage generator, which is necessary for flash memory programming and sector erasing. in other words, the S3F441FX has an internal high voltage pumping circuit, therefore, high voltage to v pp pin is not needed. instead of high voltage, md1 pins may be tied to v ss or v dd (in only mds mode). to program the data into the flash rom or sector erase in this mode, several control registers should be used, which will be explained below.
S3F441FX risc microcontroller internal flash rom 10- 3 the program procedure in the user program mode the user should write the data to be written into the data register (fmdata) and the address into the address register (fmaddr), respectively. as a next step, the user should write the values (0x5a, 0xa5, 0x5a, 0xa5 in this order) into key registers 0/1/2/3(fmkey0-3). finally, by writing the appropriate data into flash memory control register(fmucon), one word data(32-bit) can be written into flash memory at the location of the specified address and cpu will be held or working by fmacon[7] bit for 30us, which is the minimum programming time for flash memory. after the completion of the write operation, all fmkey registers and the start bit in fmucon will be cleared. to perform the next writing operation, fmkey0-3 registers and fmucon register should be written again as before. sector erase procedure is the same as program procedure except setting the flash memory data register (fmdata). you can enable three protection modes read protection, hardware protection, ld protection. tool program mode the 6 pins are connected to a tool board and programmed by serial otp tool (spw). v dd ?12.5 v should be applied to the md1 (v pp ) pin. the other modules except the internal flash rom will be in reset state. this mode does not support the sector erase. instead the chip erase is supported. three protection modes(hard lock/ld/read protection) can be enabled in this mode. address flash cell cpu fmkey0-3 fmucon fmdata fmaddr data address data data bus address data address bus address data normal flash memory interface tool program interface user program interface figure 10-1. flash memory read/write block diagram
internal flash rom S3F441FX risc microcontroller 10- 4 flash memory special registers flash memory key registers to program data into the flash memory by the user programming mode, 4-key registers with 0x5a,0xa5,0x5a and 0xa5 are required to prevent flash data from being destroyed under undesired situations. register offset r/w description access reset value fmkey0 0x3010 w flash program / erase key register0 b 00h fmkey1 0x3011 w flash program / erase key register1 b 00h fmkey2 0x3012 w flash program / erase key register2 b 00h fmkey3 0x3013 w flash program / erase key register3 b 00h note: the fmkeyn register will be cleared automatically just after the completion of erase/program. flash memory address register register offset r/w description access reset value fmaddr 0x3014 r/w flash program / sector erase address register w 0000 0000h note: to program the option sector area, set fmaddr to 0x0e38(smart option) or 0x0e3c (protection option) and fmdata by the appropriate value and start the write operation. flash memory data register register offset r/w description access reset value fmdata 0x3018 r/w flash program data register w 0000 0000h
S3F441FX risc microcontroller internal flash rom 10- 5 flash memory user programming control register the fmucon can determine the program/erase operation. in user programming mode, the S3F441FX can support only sector erase; flash memory should be programmed by a word unit. among 4 operating modes, only one operating mode can be selected. otherwise, the there will be a configuration error. in this case, clear the error register and start the operation again. register offset r/w description access reset value fmucon 0x301f r/w flash memory program/sector erase control register b 00h [0] option (protection/smart option) sector erase enable(osers) 0 = disable 1 = enable [1] normal sector erase enable (nsers) 0 = disable 1 = enable [2] option (protection/smart option) sector program enable(ospgm) 0 = disable 1 = enable [3] normal sector program enable (nspgm) 0 = disable 1 = enable [6:4] ? [7] operation start/stop 0 = stop 1 = start this bit will be cleared automatically just after the corresponding operation is completed . . the fmacon can control the access cycle for flash memory. this register setting is effective for reading flash memory. register offset r/w description access reset value fmacon 0x3027 r/w flash memory access control register b 03h [1:0] flash memory access cycles 11 = 3 cycles 10 = 2 cycle 01 = 1 cycles 00 = not used the internal flash rom access time is 50ns. so, the access cycles will be configured as follows. @ 20mhz : 1 cycle @ 40mhz : 2 cycles [6:2] reserved [7] cpu hold during flash operation 0 = cpu working during flash programming/erasing in this case, the flash programming/erasing code should not be on the internal flash rom. the completion of an operation is checked using fmucon register. the advantage is that cpu can perform other tasks until the completion of an operation. 1 = cpu hold during flash programming/erasing
internal flash rom S3F441FX risc microcontroller 10- 6 flash memory error register if an error occurs during flash memory program / erase, the corresponding bit will be set. then, user can check the error type which had occurred. register offset r/w description access reset value fmerr 0x3023 r/w flash memory error register b 01h [0] clear fmkey / fmucon 0: clear fmkey and fmucon register. 1: no operation. this bit clears the fmkeyn & fmucon registers. after the clear operation, this bit will be restored to 1, automatically. [6:1] reserved [7] configuration error(cfgerr) 0: no error 1: configuration error occurred. this bit indicates that the command is invalid in the fmucon register. ( for example, program and erase is active at the same time) note: to verify the erase/write operation, fmerr[7] will not be used. the completion of data should be verified by reading the data.
S3F441FX risc microcontroller internal flash rom 10- 7 flash memory smart option bits read register reading the smart option / protection option bits is possible only through fsoread / fporead registers because the bits of smart option / protection option cannot be read like normal cell. register offset address r/w description initial value (at fabrication) fsoread 0x3028 r smart option bits read register msb xxxx_xxx1 [31:24] xxxx_xxx1 xxxx_xxx1 lsb xxxx_xxx1b [7:0] flash memory protection option bits read register register offset address r/w description initial value (at fabrication) fporead 0x302c r protection option bits read register msb xxxx_1xxx xxxx_xx1x xxxx_xxx1 lsb xxxx_xxxxb note if any bit of fmerr register is set, the user must clear the fmerr register and write (erase) the flash memory again at first.
internal flash rom S3F441FX risc microcontroller 10- 8 fmaddr 20-bit address fmdata 32-bit data start fmkey0-3 0x5a, a5, 5a, a5 fmucon 0x08 fmucon 0x88 program finish? checksum ok? finish clear fmerr increase fmaddr fmdata 32-bit data no yes yes no ; address set ; data set ; key value set whenenver starts ; mode select & start programming ; compare end address ; error during programming ; next address/data set figure 10-2. normal sector program flowchart in a user program mode ( in the figure: "?. compare end address) start fmkey0-3 0x5a, a5, 5a, a5 fmucon 0x04 fmucon 0x84 fmerr[7] = 0? fmucon[7] = 0? finish clear fmerr yes no ; option address set ; function set ; set key value ; mode select & start programming ; error during programming ; if error, write one word again fmaddr smart option: 0x0e38 or protection option: 0x0e3c fmdata 32-bit data figure 10-3. option sector program flowchart in a user program mode
S3F441FX risc microcontroller internal flash rom 10- 9 start fmkey0-3 0x5a, a5, 5a, a5 fmucon 0x02 fmucon 0x82 fmerr[7] = 0? fmucon[7]= 0? finish clear fmerr yes no ; set key value ; mode select & start programming ; error during erasing? ; if error, erase again fmaddr 20-bit address ; set address to be erased figure 10-4. normal sector erase flowchart start fmkey0-3 0x5a, a5, 5a, a5 fmucon 0x01 fmucon 0x81 fmerr[7] = 0? fmucon[7] = 0? finish clear fmerr yes no ; set key value ; mode select & start programming ; error during erasing? ; if error, erase again fmaddr 0x0e3x ; set address to smart option figure 10-5. option sector erase flowchart
internal flash rom S3F441FX risc microcontroller 10- 10 data protection the data programmed in flash memory, need to be protected. in this case, the S3F441FX can support three kinds of protection mechanism. ? hardware protection ? read protection ? ld protection these protection modes can be enabled by the configuration in the option sector. user can select the tool program mode or the protection option bit/smart option bit in a user program mode. the protection option bits (0x0e3c) can be enabled/disabled in terms of hardware protection, read protection, and ld protection. the smart option bits (0x0e38) can adjust the area of hardware protection and ld protection. protection option protection bit table fmaddr value fmdata bit description initial value (at fabrication) 0x0e3c bit[7:0] not used undefined bit[8] 0: enable the ld protection 1: disable the ld protection 1 bit[16:9] not used undefined bit [17] 0: enable the hardware protection 1: disable the hardware protection 1 bit[26:18] not used undefined bit [27] 0: enable the read protection 1: disable the read protection 1 bit[31:28] not used undefined read protection bit 27 there are many users who do not want their data to be read by others. read protection can give the solution for this by preventing the flash data from being read serially in the tool program mode. this read protection is not available in the user program mode. when this function is enabled, the reading or and verification of flash data in the tool program mode will result in all zero read-out. read protection can be set and released in user program mode on the condition of hdp(hardware protection) released as follows. the user should write 0x0e3c into the address and the proper data 0x00ffffff(refer to the above protection bit table) into the data register (fmdata), respectively. as a next step, the user should write the values (0x5a, 0xa5, 0x5a, 0xa5 in this order) into key registers 0/1/2/3(fmkey0-3). finally, set fmucon.2(option sector program enable bit) then set fmucon.7(operation start bit). pls refer to figure 10-3(option sector program flowchart). meanwhile, in order to release read protection, the user has to erase option sector as similar as read protection process. pls refer to figure 10-5 (option sector erase flowchart), which results in initializing all protection bits and smart option bits. on the other way, the user can set read protection in tool program mode by executing its functions and release read protection by chip erase, which results in initializing all protection bits, smart option bits and erasing
S3F441FX risc microcontroller internal flash rom 10- 11 internal flash rom data, hardware protection(hard lock) bit 17 if this function is enabled, the user cannot write or erase the data in a flash memory locked area. further more cannot be set or released protection option and smart option. hard lock function affects a tool program mode as well as a user program mode. this protection can be released only by the chip erase execution in the tool program mode. refer to smart option about hard lock protection of blocks. hardware protection can be set in user program mode as follows. the user should write 0x0e3c into the address and the proper data 0xff00ffff(refer to the above protection bit table) into the data register (fmdata), respectively. as a next step, the user should write the values (0x5a, 0xa5, 0x5a, 0xa5 in this order) into key registers 0/1/2/3(fmkey0-3). finally, set fmucon.2(option sector program enable bit) then set fmucon.7(operation start bit). pls refer to figure 10-3(option sector program flowchart). on the other way, the user can set read protection in tool program mode by executing its functions and release read protection by chip erase, which results in initializing all protection bits, smart option bits and erasing internal flash rom data, ld protection bit 8 ld protection can protect the reading of data in flash memory by load instruction (all ld-relative instructions). when anyone try to read of internal flash data on ld protection enabled, the execution of ldr(load) instruction results in unknown data read-out. weather internal flash is mapped to normal operating mode(in-rom mode) or external rom mode(rom-less)mode, the ld protection is available. pls refer to more mapping details fig10-6. the user who wants to use ld protection is very careful to avoid load instructions in internal flash rom area locked by ld protection. it?s recommended not to use c-language for firmware development, because the compiler can make undesired load instructions on assembling c-code. ld protection can be set and released in user program mode on the condition of hdp(hardware protection) released as follows. the user should write 0x0e3c into the address and the proper data 0xffff00ff(refer to the above protection bit table) into the data register (fmdata), respectively. as a next step, the user should write the values (0x5a, 0xa5, 0x5a, 0xa5 in this order) into key registers 0/1/2/3(fmkey0-3). finally, set fmucon.2(option sector program enable bit) then set fmucon.7(operation start bit). pls refer to figure 10- 3(option sector program flowchart). meanwhile, in order to release ld protection, the user has to erase option sector as similar as read protection process. pls refer to figure 10-5 (option sector erase flowchart), which results in initializing all protection bits and smart option bits. on the other way, the user can set rd protection in tool program mode by executing its functions and release read protection by chip erase, which results in initializing all protection bits, smart option bits and erasing internal flash rom data,
internal flash rom S3F441FX risc microcontroller 10- 12 smart option for ld protection / h/w protection in the ld/hardware protection function, the protection on certain block can be disabled by setting the corresponding smart option bits. four bits are allocated in the address of smart option (0x0e38) for this function. to enable the protection function on a certain block, ? configure the smart option bits in advance (refer to figure 10-3), ? configure the ld protection / h/w protection option bits (0x0e3c). if the smart option bits are not configured and ldp/hdp is enabled (it has no effect ldp/hdp is not enabled), full 256k bytes flash memory will be protected. fmaddr value fmdata bit description reset value 0x0e38 bit [0] 0: h/w protection is disabled at the area of upper 248k bytes (only the lower 8k bytes are protected) 1: h/w protection is enabled in all areas if the h/w protection is enabled. 1 bit[1:7] not used undefined bit [8] 0: h/w protection is disabled at the area of upper 240k bytes. (only the lower 16k bytes are protected) if the bit[0] is 0, this bit has no effect. 1: h/w protection is enabled in all areas if the h/w protection is enabled 1 bit[9:15] not used undefined bit [16] 0: ld protection is disabled at the area of upper 248k bytes (only the lower 8k bytes are protected) 1: ld protection is enabled in all areas if the ld protection is enabled. 1 bit[17:23] not used undefined bit [24] 0: ld protection is disabled at the area of upper 240k bytes. (only the lower 16k bytes are protected) if the bit[24] is 0, this bit has no effect. 1: ld protection is enabled in all areas if the ld protection is enabled. 1 bit[25:31] not used undefined note: the flash programming tips is as follows; characteristic of flash memory cell, a bit can be changed from 1 to 0 but not the vice versa by writing data into flash memory cell. if users do not want to change the certain cell, the user only needs to write the bit as 1.
S3F441FX risc microcontroller internal flash rom 10- 13 flash memory map the S3F441FX can support two operating modes, the normal operating mode(in-rom mode) and the external rom(rom-less) mode. in the normal operating mode, the program as well as boot program should exist in the internal flash memory. in the external rom(rom-less) mode, the internal flash memory will be mapped to the other addresses as shown in the below figure. 01ff ffffh sfr area sram area 01ff 2000h 01ff 0000h external memory area flash memory area 0003 ffffh 0000 0000h 01ff ffffh sfr area sram area 01ff 2000h 01ff 0000h external memory area flash memory area 0000 0000h 8k-byte 256k-byte 01f3 ffffh 01f0 0000h 8k-byte 256k-byte figure 10-6. flash memory map according to operating mode
internal flash rom S3F441FX risc microcontroller 10- 14 tool program mode the tool program mode is the flash memory program mode, which uses an equipment such as a rom writer. if the user wants to make a dedicated flash rom writer for S3F441FX, please contact us for more detail document. table 10-1. the pins used to read/write/erase the flash rom in tool program mode pin name function name pin no. i/o function rxd/gpio15 sdat 4 i/o serial data pin.( output when reading, input when writing.) input & push-pull output port can be assigned txd/gpio14 sclk 5 i serial clock, input only (write speed: max 200 khz, read speed : max 10 mhz) md1 vpp 10 i flash cell writing power supply pin for tool program mode. the function of entering flash writing mode. when writing v dd -12.5v, when reading v dd . nreset reset 13 i chip initialization vdd/vss vdd/vss 6,7 i logic power supply pin for flash block
S3F441FX risc microcontroller system co ntrol 11- 1 11 system control power-down mode in stop mode, all logic including pll will be stopped. the external interrupts(eint0,1,2) can wake up the mcu. in idle mode, the cpu and the internal flash rom will be stopped. all enabled interrupts can wake up the mcu. global interrupt control all interrupt requests can be disabled by global interrupt control bit. pll the mclk can be programmed by pll. the pll can generate mclk up to 40mhz. pll extclk m u x /16 pll_on clksrcsel clkdivsel mclk fpllo fin utclk (uart & timer clock) /1024 /2 /8 m u x figure 11-1. clock circuit diagram
system control s3f4 41fx risc microcontroller 11- 2 extclk mclk fpllo note: the number of the clocks is depicted differently with real condition. ~ ~ ~ ~ pll lock time by the basic timer. wake-up by eint[2:0] ~ ~ stop mode by syscon[0]=1 clksrcsel=extclk clksrcsel=pll_output locktime is completed. cpu starts to operate. figure 11-2. entering & wake-up in the stop mode entering the stop mode to enter the stop mode, do the following steps. 1. set clksrcsel=extclk 2. set the syscon[0] to enter the stop mode. 3. there has to be at least 4 nop instructions following the instruction to enter the stop mode 4. pll will be turned off automatically. 5. S3F441FX is in stop mode now. exiting from the stop mode to exit from the stop mode, the following steps should be executed. to configure the stop exiting condition, configure eintmod,eintcon,intmask and syscon[8] registers. 1. eint[2:0] will be issued to exit from the stop mode. 2. pll will be turned on and the basic timer will operate to time the pll lock time. however, the pll o utput is not used for mclk until clksrcsel = pll_output is set. 3. set clksrcsel = pll_output to use fpllo as mclk. idle mode and internal flash rom in the idle mode, the internal flash rom will be stopped together. just after exiting the idle mode, the interval time(32 mclks) for start-up time of the internal flash rom should be available. this 32 mclk interval is inserted automatically by h/w logic.
S3F441FX risc microcontroller system co ntrol 11- 3 system control register the system control register(syscon) can be used to control the system operation of chip. register offset address r/w description reset value syscon 0xd002 r/w system control register 000h [0] stop bit this bit determines whether the stop mode is enabled or disabled. in stop mode, all logic including pll will be stopped. the external interrupts(eint0,1,2) can wake up mcu. this bit will be cleared automatically. [1] idle bit this bit determines whether the idle mode is enabled or disabled. in idle mode, the cpu and the internal flash rom will be stopped. all enabled interrupts can wake up mcu. this bit will be cleared automatically [2] unused [5:3] clkdivsel the clock, pll output or extclk, is divided by 1,2,8,16, or 1024. this bit determines the divide ratio. 000: 1/16, 001: 1/8, 010: 1/2 011: 1/1 100: 1/1024 [6] clksrcsel this bit determines which clock source is used, the extclk or the pll output. 0: extclk 1: pll output [7] pllon this bit determines whether the pll is turned on or off. 0: pll is turned off. 1: pll is turned on. [8] global interrupt control global interrupt enable bit. this bit can mask all interrupt request. when 0, all interrupt request will not be acceptable. 0: disable all interrupt request 1: enable the interrupt requests, which are enabled on intmask. note: to make cpu enter into stop/idle mode perfectly, there have to be 4 nop instructions after the activation of the stop or idle mode.
system control s3f4 41fx risc microcontroller 11- 4 pll (phase locked loop) the pll within the clock generator is the circuit that synchronizes the output signal with a reference or input signal in frequency as well as in phase. it is composed of the voltage controlled oscillator to generate the output frequency, the divider p to divide the reference frequency by p, the divider m to divide the vco output frequency by m, the divider s to divide the vco output frequency by s, the phase detector, charge pump, and loop filter. the output clock frequency fout is related to the reference input clock frequency fin by the following equation: fpllo = (m * fin) / (p * 2 s ) m = m (the value for divider m)+ 8, p = p(the value for divider p) + 2 the following sections describe the pll operation that includes the phase detector, charge pump, vco (voltage controlled oscillator), and loop filter. phase detector the phase detector monitors the phase difference between the fref (the reference frequency) and fvco (the output frequency), and generates a control signal when it detects difference between the two. charge pump the charge pump converts the phase detector control signal to a charge in voltage across the external filter that drives the vco. loop filter the control signal that the phase detector generates for the charge pump may generate large excursions(ripples) each time the vco output is compared to the system clock. to avoid overloading the vco, a low pass filter samples and filters the high-frequency components out of the control signal. the filter is typically a single-pole rc filter consisting of a resistor and capacitor. a recommended external loop filter capacitance is 700pf. voltage controlled oscillator (vco) the output voltage from the loop filter drives the vco, causing its oscillation frequency to increase or decrease as a function of variations in voltage. when the vco output matches the system clock in frequency and phase, the phase detector stops sending a control signal to the charge pump, which in turn stabilizes the input voltage to the loop filter. the vco frequency then remains constant, and the pll remains locked onto the system clock. divider p fin m[7:0] s[1:0] pwrdn pfd divider m p[5:0] f vco pump vco divider s f ref fpllo loop filter r 700pf c internal pllcap external figure 11-3. pll (phase-locked loop) block diagram
S3F441FX risc microcontroller system co ntrol 11- 5 pll control register (pllcon) fpllo = (m * fin) / (p * 2 s ) m = (mdiv + 8), p = (pdiv + 2), s = sdiv register offset address r/w description reset value pllcon 0xd004 r/w pll configuration register 38080 h pllcon bit description initial state mdiv [19:12] main divider control 0x38 pdiv [9:4] pre-divider control 0x08 sdiv [1:0] post divider control 0x0 note: the fpllo range is 20mhz?40mhz. pll value selection guide 1. fpllo * 2 s has to be less than 170 mhz. 2. s is as great as possible. 3. (fin / p) is recommended to be 1mhz or above. but, (fin / p) < 2mhz. pll value change steps if the pll setting needs to be changed when fpllo is used as mclk, the pll transition noise may be asserted to cpu core. so, the pll configuration has to be changed in slow mode. do the following steps to change the pll configuration. 1. set clksrcsel=extclk 2. set pms value of pll 3. wait for at least 150us. 4. set clksrcs el=pll output capacitor for pll loop filter a 700pf(same or slightly bigger) capacitor is connected between pllcap pin and vss. this capacitor will operate as a pll loop filter. pllcap 700pf figure 11-4. capacitor for pll loop filter
S3F441FX risc microcontroller special f unction registers 12- 1 12 special function re gisters overview this chapter describes the S3F441FX special function registers. 64kb sfr block has an 8kb sram area for stack or data memory and special registers to control peripheral blocks. internal 256kb flash rom cs1 (external memory) cs2 (external memory) 8kb internal sram special function registers 0x00000000 0x0003ffff 0x00800000 0x0083ffff 0x00c00000 0x00c3ffff 0x01ff0000 0x01ff2000 0x01ffffff figure 12-1. S3F441FX default memory map of the normal mode(in-rom mode) sram (8kb) peripheral control registers 0000h (offset) 1fffh (offset) ffffh (offset) 2000h (offset) figure 12-2. special function register
special function s3 f441fx risc microcontroller 12- 2 S3F441FX special registers table 12-1. S3F441FX special registers group registers offset r/w description access reset value system syscfg 0x3000 r/w system configuration register w 1ff1h manager memcon0 0x4000 r/w memory bank 0 control register w 0800 3000h memcon1 0x4004 r/w memory bank 1 control register w 0c08 3000h memcon2 0x4008 r/w memory bank 2 control register w 100c 3000h internal fmkey0 0x3010 w flash program/erase key register0 b 00h flash fmkey1 0x3011 w flash program/erase key register1 b 00h rom fmkey2 0x3012 w flash program/erase key register2 b 00h fmkey3 0x3013 w flash program/erase key register3 b 00h fmaddr 0x3014 r/w flash user program address register w 0 0000h fmdata 0x3018 r/w flash user program data register w 0000 0000h fmucon 0x301f r/w flash program/erase control register b 00h fmacon 0x3027 r/w flash access cycle control register b 03h fmerr 0x3023 r/w flash error register b 01h fsoread 0x3028 r smart option bits read register w 1b,1b,1b,1b fporead 0x302c r protection option bits read register w 1b,1b,1b uart lcon 0x5003 r/w uart line control register b 00h ucon 0x5007 r/w uart control register b 00h ussr 0x500b r uart status register b c0h tbr 0x500f w uart transmit buffer control register b xxh rbr 0x5013 r uart receive buffer control register b xxh ubrdr 0x5016 r/w uart baud rate divisor register h 0000h note: b: byte (8-bit), h: half-word (16-bit), w: word (32-bit)
S3F441FX risc microcontroller special f unction registers 12- 3 table 12-1. S3F441FX special registers (continued) group registers offset r/w description access reset value timer 0 t0data 0x9000 r/w timer 0 data register h ffffh t0pre 0x9002 r/w timer 0 prescaler register b ffh t0con 0x9003 r/w timer 0 control register b 00h t0cnt 0x9006 r timer 0 counter register h 0000h timer 1 t1data 0x9010 r/w timer 1 data register h ffffh t1pre 0x9012 r/w timer 1 prescaler register b ffh t1con 0x9013 r/w timer 1 control register b 00h t1cnt 0x9016 r timer 1 counter register h 0000h timer 2 t2data 0x9020 r/w timer 2 data register h ffffh t2pre 0x9022 r/w timer 2 prescaler register b ffh t2con 0x9023 r/w timer 2 control register b 00h t2cnt 0x9026 r timer 2 counter register h 0000h timer 3 t3data 0x903 0 r/w timer 3 data register h ffffh t3pre 0x9032 r/w timer 3 prescaler register b ffh t3con 0x9033 r/w timer 3 control register b 0000h t3cnt 0x9036 r/w timer 3 counter register h 00h timer 4 t4data 0x904 0 r/w timer 4 data register h ffffh t4pre 0x9042 r/w timer 4 prescaler register b ffh t4con 0x9043 r/w timer 4 control register b 00h t4cnt 0x9046 r/w timer 4 counter register h 0000h timer 5 t5data 0x905 0 r/w timer 5 data register h ffffh t5pre 0x9052 r/w timer 5 prescaler register b ffh t5con 0x9053 r/w timer 5 control register b 00h t5cnt 0x9056 r/w timer 5 counter register h 0000h
special function s3 f441fx risc microcontroller 12- 4 table 12-1. S3F441FX special registers (continued) group registers offset r/w description access reset value bt & btcon 0xa002 r/w basic timer control register h/b 0000h wdt btcnt 0xa007 r basic timer counter register b 00h i/o port p0 0xb000 r/w port 0 data register b xxh p1 0xb001 r/w port 1 data register b xxh p2 0xb002 r/w port 2 data register b xh eintcon 0xb018 r/w port 2 external interrupt control register b 0h eintmod 0xb01a r/w port 2 external interrupt mode register b 00h i/o port p0con 0xb010 r/w port 0 control register b 00h control p1con 0xb012 r/w port 1 control register h 0000h register p2con 0xb014 r/w port 2 control register b 0h i/o port p0pur 0xb015 r/w port 0 pull-up resister control register b 00h resistor p1pudr 0xb016 r/w port 1 pull-up/down resister control. b ffh control p2pur 0xb017 r/w port 2 pull-up resister control register b ffh interrupt intmode 0xc000 r/w interrupt mode register w xxx0 0000h contro- intpend 0xc004 r/w interrupt pending register w xxx0 0000h ller intmask 0xc008 r/w interrupt mask register w xxx0 0000h system syscon 0xd002 r/w system control register h 000h control pllcon 0xd004 r/w system control register w 38080h internal sram sram 0x0000 ? 0x1fff r/w internal 8kb sram area b,h,w xxh
S3F441FX risc microcontroller electrica l data 13- 1 13 electrical data dc electrical characteristics table 13-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd / v dda ? - 0.3 to + 3.8 v input voltage v in1 all ports except v in2 - 0.3 to v dd + 0.3 v i in dc input current ? 10 ma storage temperature t stg ? - 40 to + 125 c
electrical data s3f 441fx risc microcontroller 13- 2 table 13-2. d.c. electrical characteristics (t a = 0 c to + 70 c, v dd = 3.3 0.3v ) parameter symbol conditions min typ max unit operating voltage v dd fosc = 40mhz, 64 pins 3.0 ? 3.6 v operating temperature t a 0 ? 70 c high level input voltage 1 v ih1 nreset 0.8v dd ? ? v high level input voltage 2 v ih2 schmitt pad 2.2 ? ? v high level input voltage 2 v ih3 md0, md1 2.2 ? ? v high level input voltage 4 v ih4 cmos pad 2.0 ? ? v high level input voltage 5 v ih5 extclk v dd -0.3 ? ? v low level input voltage 1 v il1 nreset ? ? 0.2v dd v low level input voltage 2 v il2 schmitt pad ? ? 0.8 v low level input voltage 2 v il3 md0, md1 ? ? 0.6 v low level input voltage 4 v il4 cmos pad ? ? 0.8 v low level input voltage 5 v il5 extclk ? ? 0.4 v high level input current 1 i ih1 v in =3.6, no pull-down resistor -10 ? 10 ua high level input current 2 i ih2 v in =3.6, with pull-down resistor 10 ? 90 ua low level input current 1 i il1 v in =0, no pull-up resistor -10 ? 10 ua low level input current 2 i il2 v in =0, with pull-up resistor -90 ? -10 ua high level output voltage 1 v oh1 v dd =3.3v, i oh =-8ma port0,port1, port2,a0-a11,ncs, noe,nwe 2.4 ? ? v high level output voltage 2 v oh2 v dd =3.3v,i oh =-12ma, d0-d7 2.4 ? ? v low level output voltage 1 v ol1 v dd =3.3v, i oh =8ma port0, port1, port2, a0-a11,ncs, noe,nwe ? ? 0.4 v low level output voltage 2 v ol2 v dd =3.3v, i oh =12ma, d0-d7 ? ? 0.4 v operating current i dd1 v dd =3.6v, fosc=40mhz ? ? 50 ma idle mode current i dd2 v dd =3.6v, fosc=40mhz ? ? 10 ma stop mode current i dd3 v dd =3.6v ? 0.5 1 ma
S3F441FX risc microcontroller electrica l data 13- 3 vdd(v) 70 60 50 40 30 20 10 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.5 3.4 3.6 0 mclk(mhz) 2.4 2.5 3.7 3.8 spec. guaranteed area figure 13-1. typical operating frequency and voltage range ( internal flash t acc =1 ) vdd(v) 70 60 50 40 30 20 10 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.5 3.4 3.6 0 mclk(mhz) spec. guaranteed area 2.4 2.5 3.7 3.8 figure 13-2. typical operating frequency and voltage range ( internal flash t acc =2 )
electrical data s3f 441fx risc microcontroller 13- 4 table 13-3. typical quiescent supply current on v dd @normal mode, flash tacc=1 (unit: ma) vdd \ mclk 10mhz 20mhz 3.0 v 14 20 3.3 v 17 24 3.6 v 21 28 note: the above current measurement is done in the case that the code is running on internal flash rom(tacc=1) & internal sram. table 13-4. typical quiescent supply current on v dd @normal mode, flash tacc=2 (unit: ma) vdd \ mclk 30mhz 40mhz 3.0 v 21 25 3.3 v 25 29 3.6 v 29 34 note: the above current measurement is done in the case that the code is running on internal flash rom(tacc=2) & internal sram. table 13-5. typical quiescent supply current on v dd @idle mode (unit: ma) vdd \ mclk 10mhz 20mhz 30mhz 40mhz 3.0 v 1.9 3.0 3.3 4.1 3.3 v 2.2 3.4 3.8 4.8 3.6 v 2.5 3.9 4.3 5.5 notes: 1. the above current measurement is done in the case that the code is on internal flash rom & internal sram. 2. the idle mode current consumption is independent to the internal flash memory tacc.
S3F441FX risc microcontroller electrica l data 13- 5 ac electrical characteristics extclk mclk (internal clock) t mclkdly figure 13-3. extclk and mclk (internal clock) when pll is not used. note: in the figure 13-1, mclk is the simulated waveform for the case of not using pll. because the mclk can't be shown, all the timing diagram should be drawn only for the case that extclk is signaled by an external clock source without using pll. also, all the timing diagram are drawn using t he extclk instead of mclk as a reference clock because only the extclk can be shown.
electrical data s3f 441fx risc microcontroller 13- 6 extclk ncs addr noe nwait data(r) t addr t ncs t ncs t noe t noe t addr 'h' t ds t dh figure 13-4. sram read access timing without nwait ( t cos =1,t acs =0,t coh =0,t acc =3 ) extclk ncs addr noe nwait data(r) t addr t ncs t ncs t noe t noe t addr t ds t dh 2 wait cycle t acc = 3 t nwth t nwts t nwts nwait sampling points figure 13-5. sram read access timing with nwait ( t cos =1, t acs =0, t coh =0, t acc =3, external wait=2 )
S3F441FX risc microcontroller electrica l data 13- 7 extclk ncs addr nwe nwait data(w) t addr t ncs t ncs t nwe t nwe t addr 'h' t wd t w d t acc = 3 figure 13-6. sram write access timing without nwait ( t cos =1, t acs =0, t coh =0, t acc =3 ) extclk ncs addr nwe nwait data(w) t addr t ncs t ncs t nwe t nwe t addr t wd 2 wait cycle t acc = 3 t nwth t nwts t nwts nwait sampling points t wd figure 13-7. sram write access timing with nwait ( t cos =1, t acs =0, t coh =0, t acc =3, external wait=2 )
electrical data s3f 441fx risc microcontroller 13- 8 extclk ncs addr noe nwait data(r) 2 wait cycle t acc = 3 nwait sampling points t acs = 1 t coh = 1 figure 13-8. sram read access timing with nwait (t cos =0, t acs =1, t coh =1, t acc =3, external wait=2) extclk ncs addr noe nwait data(r) 2 wait cycle t acc = 3 nwait sampling points t acs = 1 figure 13-9. sram read access timing with nwait at the last cycle of half-word/word access and byte access (t cos =0, t acs =1, t coh =0, t acc =3, external wait=2)
S3F441FX risc microcontroller electrica l data 13- 9 extclk ncs addr noe nwait 2 wait cycle t acc = 3 nwait sampling points t acs = 1 data(r) figure 13-10. sram read access timing with nwait during half-word/word access, except the last cycle (t cos =0, t acs =1, t coh =0, t acc =3, external wait=2) notes: 1. external nwait is synchronized at the falling edge of extclk. that is, cpu recognizes the internal nwait as external memory wait signal. 2. internal cpu fetches the data at the falling edge of internal clock, mclk. extclk nwait data(r) (1) internal nwait mclk (internal clock) (2) data fetch time figure 13-11. nwait data fetch timing
electrical data s3f 441fx risc microcontroller 13- 10 table 13-6. timing constants (v dd = 3.3 0.3v, t a = 0 to 70 o c, operating frequency = 40 mhz) parameter symbol min typ max unit extclk input frequency when not using pll f extclk 0 ? 40 mhz extclk input frequency for pll f pllin 4 ? 20 extclk to mclk delay time t mclkdly 5 ns address delay time t addr ? 22 ncs (chip select) delay time t ncs ? 17 noe (read enable) delay time t noe ? 17 nwe (write enable) delay time t nwe ? 17 nwait sampling setup time t nwts 0 ? nwait sampling hold time t nwth 10 ? write data delay time t wd ? 17 data setup time t ds 0 data hold time t dh 10 table 13-7. ac electrical characteristics for internal flash rom (t a = 0 c to + 70 c , v dd = 3.0 v to 3.6v) parameter symbol conditions min typ max unit programming time (1) ftp v dd = 3.3v 20 30 50 us chip erasing time (2) ftp1 ? 10 20 ms sector erasing time (3) ftp2 ? 2 3 ms data access time ft rs ? 40 ? ns number of writing / erasing fnwe ? ? 1,000 times notes: 1. the programming time is the time during which one word (32-bit) is programmed. 2. the chip erasing time is the time during which all 256k-byte block is erased. 3. the sector erasing time is the time during which all 512-byte block is erased. 4. the chip erasing is available in tool program mode only.
S3F441FX risc microcontroller mechanica l data 14- 1 14 mechanical data package dimensions 64-lqfp-1010-an #64 10.00 bsc 12.00 bsc 10.00 bsc 12.00 bsc #1 0.50 bsc 0.20 + 0.07 - 0.03 0.45-0.75 1.60 max 0.08 max 0.09-0.20 0-7 1.40 0.05 0.10 0.05 0.08 max figure 14-1. 64-lqfp-1010 package dimensions (unit: mm)
(for duplicate copies of this form, and for additional ordering information, please contact your local sa m sung sales representative. samsung sales offices are listed on the back cover of this book.) s3f series mask rom order form product description: device number: s3f__________- ___________(write down the rom code number) product order form: package pellet wafer package type: __________ package marking (check one): standard custom a custom b (max 10 chars) (max 10 chars each line) @ : assembly site code, y : last number of assembly year, ww : week of assembly @ yww device name sec device name @ yww @ yww delivery dates and quantities: deliverable required delivery date quantity comments rom code ? not applicable see rom selection form customer sample risk order see risk order sheet please answer the following questions: + + for what kind of product will you be using this order? new product upgrade of an existing product replacement of an existing product other if you are replacing an existing product, please indicate the former product name ( ) + + what are the main reasons you decided to use a samsung microcontroller in your product? please check all that apply. price product quality features and functions development system technical support delivery on time used same micom before quality of documentation samsung reputation mask charge (us$ / won): ____________________________ customer information: company name: ___________________ telephone number _________________________ signatures: ________________________ __________________________________ (person placing the order) (technical manager)

(for duplicate copies of this form, and for additional ordering information, please contact your local sa m sung sales representative. samsung sales offices are listed on the back cover of this book.) s3f series request for production at customer risk customer information: company name: ________________________________ ________________________________ department: ________________________________________________________________ telephone number: __________________________ fax: _____________________________ date: __________________________ risk order information: device number: s3f________- ________ (write down the rom code number) package: number of pins: ____________ package type: _____________________ intended application: ________________________________________________________________ product model number: _________ _______________________________________________________ customer risk order agreement: we hereby request sec to produce the above named product in the quantity stated below. we believe our risk order product to be in full compliance with all sec production specifications and, to this extent, agree to assume responsibility for any and all production risks involved. order quantity and delivery schedule: risk order quantity: _____________________ pcs delivery schedule: delivery date (s) quantity comments signatures: _______________________________ _________________________________ _____ _ (person placing the risk order) (sec sales representative)

(for duplicate copies of this form, and for additional ordering information, please contact your local sa m sung sales representative. samsung sales offices are listed on the back cover of this book.) S3F441FX mask option selection form device number: S3F441FX -__________(write down the rom code number) attachment (check one): diskette prom customer checksum: ________________________________________________________________ company name: ________________________________________________________________ signature (engineer): ________________________________________________________________ please answer the following questions: + + application ( product model id: _______________________) audio video telecom lcd databank caller id lcd game industrials home appliance office a utomation remocon other please describe in detail its application ___________________________________________________________________________

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